型号 功能描述 生产厂家 企业 LOGO 操作

High Performance E2CMOS PLD Generic Array Logic

Description The GAL16V8, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times ( Features •HIGH PERFORMANCE

Lattice

莱迪思

All Devices Discontinued

Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on

Lattice

莱迪思

High Performance E2CMOS PLD Generic Array Logic

Description The GAL16V8, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times ( Features •HIGH PERFORMANCE

Lattice

莱迪思

All Devices Discontinued

Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on

Lattice

莱迪思

All Devices Discontinued

Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on

Lattice

莱迪思

All Devices Discontinued

Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on

Lattice

莱迪思

All Devices Discontinued

Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on

Lattice

莱迪思

High Performance E2CMOS PLD Generic Array Logic

Description The GAL16V8, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times ( Features •HIGH PERFORMANCE

Lattice

莱迪思

High Performance E2CMOS PLD Generic Array Logic

Description The GAL16V8, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times ( Features •HIGH PERFORMANCE

Lattice

莱迪思

All Devices Discontinued

Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on

Lattice

莱迪思

All Devices Discontinued

Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on

Lattice

莱迪思

All Devices Discontinued

Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on

Lattice

莱迪思

All Devices Discontinued

Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on

Lattice

莱迪思

High Performance E2CMOS PLD Generic Array Logic

Description The GAL16V8, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times ( Features •HIGH PERFORMANCE

Lattice

莱迪思

High Performance E2CMOS PLD Generic Array Logic?

文件:293.59 Kbytes Page:8 Pages

Lattice

莱迪思

High Performance E2CMOS PLD Generic Array Logic?

文件:339.82 Kbytes Page:23 Pages

Lattice

莱迪思

High Performance E2CMOS PLD

文件:340.72 Kbytes Page:23 Pages

Lattice

莱迪思

High Performance E2CMOS PLD Generic Array Logic?

文件:395.51 Kbytes Page:22 Pages

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莱迪思

High Performance E2CMOS PLD Generic Array Logic?

文件:654.14 Kbytes Page:24 Pages

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莱迪思

IC CPLD 8MC 7.5NS 20PLCC

Lattice

莱迪思

High Performance E2CMOS PLD Generic Array Logic?

文件:395.51 Kbytes Page:22 Pages

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莱迪思

High Performance E2CMOS PLD Generic Array Logic?

文件:339.82 Kbytes Page:23 Pages

Lattice

莱迪思

High Performance E2CMOS PLD

文件:340.72 Kbytes Page:23 Pages

Lattice

莱迪思

High Performance E2CMOS PLD Generic Array Logic?

文件:654.14 Kbytes Page:24 Pages

Lattice

莱迪思

High Performance E2CMOS PLD

文件:340.72 Kbytes Page:23 Pages

Lattice

莱迪思

High Performance E2CMOS PLD Generic Array Logic?

文件:654.14 Kbytes Page:24 Pages

Lattice

莱迪思

封装/外壳:20-LCC(J 形引线) 包装:管件 描述:IC CPLD 8MC 7.5NS 20PLCC 集成电路(IC) CPLD(复杂可编程逻辑器件)

ETC

知名厂家

IC CPLD 8MC 7.5NS 20PLCC

Lattice

莱迪思

封装/外壳:20-LCC(J 形引线) 包装:管件 描述:IC CPLD 8MC 7.5NS 20PLCC 集成电路(IC) CPLD(复杂可编程逻辑器件)

ETC

知名厂家

High Performance E2CMOS PLD Generic Array Logic?

文件:654.14 Kbytes Page:24 Pages

Lattice

莱迪思

High Performance E2CMOS PLD Generic Array Logic?

文件:654.14 Kbytes Page:24 Pages

Lattice

莱迪思

High Performance E2CMOS PLD Generic Array Logic?

文件:395.51 Kbytes Page:22 Pages

Lattice

莱迪思

High Performance E2CMOS PLD Generic Array Logic?

文件:339.82 Kbytes Page:23 Pages

Lattice

莱迪思

High Performance E2CMOS PLD

文件:340.72 Kbytes Page:23 Pages

Lattice

莱迪思

High Performance E2CMOS PLD

文件:340.72 Kbytes Page:23 Pages

Lattice

莱迪思

High Performance E2CMOS PLD Generic Array Logic?

文件:654.14 Kbytes Page:24 Pages

Lattice

莱迪思

High Performance E2CMOS PLD Generic Array Logic?

文件:339.82 Kbytes Page:23 Pages

Lattice

莱迪思

High Performance E2CMOS PLD Generic Array Logic?

文件:395.51 Kbytes Page:22 Pages

Lattice

莱迪思

High Performance E2CMOS PLD Generic Array Logic?

文件:654.14 Kbytes Page:24 Pages

Lattice

莱迪思

High Performance E2CMOS PLD

文件:340.72 Kbytes Page:23 Pages

Lattice

莱迪思

High Performance E2CMOS PLD Generic Array Logic?

文件:654.14 Kbytes Page:24 Pages

Lattice

莱迪思

High Performance E2CMOS PLD Generic Array Logic?

文件:293.59 Kbytes Page:8 Pages

Lattice

莱迪思

High Performance E2CMOS PLD

文件:340.72 Kbytes Page:23 Pages

Lattice

莱迪思

High Performance E2CMOS PLD Generic Array Logic?

文件:339.82 Kbytes Page:23 Pages

Lattice

莱迪思

High Performance E2CMOS PLD Generic Array Logic?

文件:654.14 Kbytes Page:24 Pages

Lattice

莱迪思

GAL16V8D-7L产品属性

  • 类型

    描述

  • 型号

    GAL16V8D-7L

  • 制造商

    LATTICE

  • 制造商全称

    Lattice Semiconductor

  • 功能描述

    High Performance E2CMOS PLD Generic Array Logic

更新时间:2025-12-23 18:08:00
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
LATTICE
20+
PLCC20
35830
原装优势主营型号-可开原型号增税票
LEGERITY
2025+
PLCC
4119
全新原装、公司现货热卖
LATTICE/莱迪斯
2450+
PLCC-20
8850
只做原装正品假一赔十为客户做到零风险!!
LATTICE
24+
PLCC20
1000
原装正品现货
LAT
25+23+
PLCC-20
37415
绝对原装正品全新进口深圳现货
LAT
25+
PLCC-20
3200
全新原装、诚信经营、公司现货销售
Lattice
24+
PLCC20
200
LATTICE
25+
5
公司优势库存 热卖中!
LAT
22+
PLCC-20
2000
进口原装!现货库存
LATTICE
05+
原厂原装
4492
只做全新原装真实现货供应

GAL16V8D-7L数据表相关新闻