位置：首页 > IC中文资料第5562页 > GAL16V8D-10
| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
High Performance E2CMOS PLD Generic Array Logic Description The GAL16V8, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times ( Features •HIGH PERFORMANCE | Lattice 莱迪思 |   | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic Description The GAL16V8, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times ( Features •HIGH PERFORMANCE | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic Description The GAL16V8, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times ( Features •HIGH PERFORMANCE | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic Description The GAL16V8, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times ( Features •HIGH PERFORMANCE | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic Description The GAL16V8, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times ( Features •HIGH PERFORMANCE | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic Description The GAL16V8, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times ( Features •HIGH PERFORMANCE | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic Description The GAL16V8, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times ( Features •HIGH PERFORMANCE | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic? 文件：293.59 Kbytes Page：8 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic? 文件：654.14 Kbytes Page：24 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic? 文件：395.51 Kbytes Page：22 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic? 文件：339.82 Kbytes Page：23 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD 文件：340.72 Kbytes Page：23 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD 文件：340.72 Kbytes Page：23 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic? 文件：654.14 Kbytes Page：24 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic? 文件：339.82 Kbytes Page：23 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic? 文件：395.51 Kbytes Page：22 Pages | Lattice 莱迪思 | | ||
封装/外壳：20-LCC（J 形引线） 包装：管件 描述：IC CPLD 8MC 10NS 20PLCC 集成电路（IC） CPLD（复杂可编程逻辑器件） | ETC 知名厂家 | ETC | | |
封装/外壳：20-LCC（J 形引线） 包装：托盘 描述：IC CPLD 8MC 10NS 20PLCC 集成电路（IC） CPLD（复杂可编程逻辑器件） | ETC 知名厂家 | ETC | | |
High Performance E2CMOS PLD Generic Array Logic? 文件：654.14 Kbytes Page：24 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD 文件：340.72 Kbytes Page：23 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic? 文件：654.14 Kbytes Page：24 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic? 文件：395.51 Kbytes Page：22 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD 文件：340.72 Kbytes Page：23 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic? 文件：654.14 Kbytes Page：24 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic? 文件：339.82 Kbytes Page：23 Pages | Lattice 莱迪思 | | ||
IC CPLD 8MC 10NS 20DIP | Lattice 莱迪思 | | ||
IC CPLD 8MC 10NS 20DIP | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic? 文件：395.51 Kbytes Page：22 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic? 文件：339.82 Kbytes Page：23 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD 文件：340.72 Kbytes Page：23 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic? 文件：654.14 Kbytes Page：24 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD 文件：340.72 Kbytes Page：23 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic? 文件：654.14 Kbytes Page：24 Pages | Lattice 莱迪思 | | ||
IC CPLD 8MC 10NS 20DIP | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic? 文件：654.14 Kbytes Page：24 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic? 文件：293.59 Kbytes Page：8 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic? 文件：339.82 Kbytes Page：23 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic? 文件：654.14 Kbytes Page：24 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD 文件：340.72 Kbytes Page：23 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD 文件：340.72 Kbytes Page：23 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic? 文件：339.82 Kbytes Page：23 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic? 文件：654.14 Kbytes Page：24 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic? 文件：395.51 Kbytes Page：22 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic? 文件：654.14 Kbytes Page：24 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD 文件：340.72 Kbytes Page：23 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD 文件：340.72 Kbytes Page：23 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic? 文件：339.82 Kbytes Page：23 Pages | Lattice 莱迪思 | |
GAL16V8D-10产品属性
- 类型
描述
- 型号
GAL16V8D-10
- 制造商
LATTICE
- 制造商全称
Lattice Semiconductor
- 功能描述
High Performance E2CMOS PLD Generic Array Logic
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
LATTICE/莱迪斯 |
22+ |
PLCC |
100000 |
代理渠道/只做原装/可含税 |
|||
LATTE/莱迪斯 |
24+ |
NA/ |
327 |
优势代理渠道,原装正品,可全系列订货开增值税票 |
|||
LATTICE |
25+ |
PLCC20 |
347 |
原装正品,假一罚十! |
|||
LATTICE |
1043+ |
PLCC20 |
327 |
一级代理,专注军工、汽车、医疗、工业、新能源、电力 |
|||
LATTICE |
22+ |
PLCC-20 |
5000 |
只做原装,假一赔十 |
|||
LATTICE |
2023+ |
PLCC-20 |
3000 |
进口原装现货 |
|||
LATTICE |
24+ |
SOIC |
3600 |
只做原装正品现货 欢迎来电查询15919825718 |
|||
LATTICE |
24+ |
PLCC20 |
1000 |
原装正品现货 |
|||
LATTICE |
25+ |
SOIC-20P |
9000 |
百分百原装正品 真实公司现货库存 本公司只做原装 可 |
|||
17+ |
6200 |
100%原装正品现货 |
GAL16V8D-10规格书下载地址
GAL16V8D-10参数引脚图相关
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- GAG01Z
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GAL16V8D-10数据表相关新闻
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搜索： SMD/SMT SPLD - 简单可编程逻辑器件 , TSSOP-20 SPLD - 简单可编程逻辑器件 , TSSOP-20 SPLD - 简单可编程逻辑器件 , STQFN-12 SPLD - 简单可编程逻辑器件
2020-7-13GAL16V8D-15LD/883产品规格参数
GAL16V8D-15LD/883
2020-7-10GAL16V8D-15LD/883
SPLD - 简单可编程逻辑器件
2019-12-18
DdatasheetPDF页码索引
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