General Description

These P-Channel logic level enhancement mode power field effect transistors are produced using Fairchilds proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage applications such as DC/DC converters and high efficiency switchingcircuits where fast switching, low in-line power loss, and resistance to transients are needed.

Features

-30 A, -30 V. RDS(ON)= 0.042 W@ VGS= -4.5V

RDS(ON)= 0.025 W@ VGS= -10 V.

Critical DC electrical parameters specified at elevated temperature.

Rugged internal source-drain diode can eliminate the need for an external Zener diode transient suppressor.

High density cell designfor extremely low RDS(ON).

175°C maximum junction temperature rating.