5V LVDS 4-Bit High Speed Differential Receiver

General Description This quad receiver is designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. The receiver translates LVDS levels, with a typical differential input threshold of 100 mV, to LVTTL signal levels. LVDS provides low EMI at ultra low po

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 包装：卷带（TR） 描述：IC RECEIVER 0/4 16SOIC 集成电路（IC） 驱动器，接收器，收发器

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 包装：管件 描述：IC RECEIVER 0/4 16SOIC 集成电路（IC） 驱动器，接收器，收发器

5V LVDS 4-Bit High Speed Differential Receiver

General Description This quad receiver is designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. The receiver translates LVDS levels, with a typical differential input threshold of 100 mV, to LVTTL signal levels. LVDS provides low EMI at ultra low po

5V LVDS 4-Bit High Speed Differential Receiver

General Description This quad receiver is designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. The receiver translates LVDS levels, with a typical differential input threshold of 100 mV, to LVTTL signal levels. LVDS provides low EMI at ultra low po

5V LVDS 4-Bit High Speed Differential Receiver

General Description This quad receiver is designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. The receiver translates LVDS levels, with a typical differential input threshold of 100 mV, to LVTTL signal levels. LVDS provides low EMI at ultra low po

400mA SmartLDOTM with Internal Pass MOSFET

DESCRIPTION Intended for applications such as Power Managed PCI, the SC1532 is designed to maintain a glitch-free 3.3V output when at least one of two inputs, 5V (VIN1) and 3.3V (VIN2), is present. FEATURES • Glitch-free transition between input sources • Internal logic selects input source •

400mA SmartLDOTM with Internal Pass MOSFET

DESCRIPTION Intended for applications such as Power Managed PCI, the SC1532 is designed to maintain a glitch-free 3.3V output when at least one of two inputs, 5V (VIN1) and 3.3V (VIN2), is present. FEATURES • Glitch-free transition between input sources • Internal logic selects input source •