Description

The EDS1232AA is a 128M bits SDRAM organized as 1,048,576 words ×32 bits ×4 banks. All inputs and outputs are synchronized with the positive edge of the clock.

Features

• 3.3V power supply

• Clock frequency: 166MHz (max.)

• Single pulsed /RAS

• ×32 organization

• 4 banks can operate simultaneously and independently

• Burst read/write operation and burst read/single write operation capability

• Programmable burst length (BL): 1, 2, 4, 8 and full page

• 2 variations of burst sequence

 Sequential (BL = 1, 2, 4, 8, full page)

 Interleave (BL = 1, 2, 4, 8)

• Programmable /CAS latency (CL): 2, 3

• Byte control by DQM

• Refresh cycles: 4096 refresh cycles/64ms

• 2 variations of refresh

 Auto refresh

 Self refresh

• FBGA(µBGA) package with lead free solder (Sn-Ag-Cu)