SDP-K1 Controller Board

GENERAL DESCRIPTION This user guide describes the EVAL-SDP-CK1Z (SDP-K1) controller board from Analog Devices, Inc., and provides instructions on the setup of the SDP-K1 board to begin USB communication to a PC. The SDP-K1 controller board is a part of the evaluation system for many Analog Devic

32 μA, Ultra-Low Power, 24-Bit Sigma-Delta ADC with Integrated PGA and FIFO

FEATURES ► Ultra-low current consumption (typical) ► 32 μA: continuous conversion mode (gain = 128) ► 5 μA: duty cycling mode (ratio = 1/16) ► 0.5 μA: standby mode ► 0.1 μA: power-down mode ► Built-in features for system level power savings ► Current saving duty cycle ratio: 1/4 or 1/16 ►

32 μA, Ultra-Low Power, 16-Bit Sigma-Delta ADC with Integrated PGA and FIFO

FEATURES ► Ultra-low current consumption (typical) ► 32 μA: continuous conversion mode (gain = 128) ► 5 μA: duty cycling mode (ratio = 1/16) ► 0.5 μA: standby mode ► 0.1 μA: power-down mode ► Built-in features for system level power savings ► Current saving duty cycle ratio: 1/4 or 1/16 ►

24-Bit, 62.5kSPS, Multichannel, Low-Noise Precision Sigma-Delta ADC

FEATURES ► Input referred noise: 10nV at 3.8SPS, Gain = 128 ► Crosspoint multiplexed analog inputs ► 4 Differential/8 Pseudodifferential inputs ► Ultra-low noise integrated PGA, gains of 0.5 to 128 ► Output data rate: 3.8SPS to 62.5kSPS ► Flexible digital filters ► Low latency sinc filters

24-Bit, 62.5kSPS, Multichannel, Low-Noise Precision Sigma-Delta ADC

FEATURES ► Input referred noise: 10nV at 3.8SPS, Gain = 128 ► Crosspoint multiplexed analog inputs ► 4 Differential/8 Pseudodifferential inputs ► Ultra-low noise integrated PGA, gains of 0.5 to 128 ► Output data rate: 3.8SPS to 62.5kSPS ► Flexible digital filters ► Low latency sinc filters

包装：盒 描述：SDP-K1 CONTROLLER BOARD 开发板，套件，编程器 配件