Programmable Logic Device Family

General Description The MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counte

Programmable Logic Device Family

General Description The MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counte

Programmable Logic Device Family

General Description The MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counte

Programmable Logic Device Family

General Description The MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counte

EPM7064STC44-10N - 芯片, 可编程逻辑器件 MAX ISP PLD

The EPM7064STC44-10N is a high-density, high-performance Programmable Logic Device (PLD) based on second-generation MAX® architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5000 usable gates, ISP, pin-to-pin delays as fast as 5ns and counter speed ·Built-in JTAG boundary-scan test\n·PCI-compliant devices available\n·5ns pin-to-pin logic delays with up to 175.4MHz counter frequencies\n·Open-drain output option\n·Programmable macrocell flip-flops with individual clear, preset, clock and clock enable controls\n·Programmable power-saving mode for;

Programmable Logic Device Family

General Description The MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counte

Programmable Logic Device Family

General Description The MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counte

Programmable Logic Device Family

General Description The MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counte

封装/外壳：100-TQFP 包装：托盘 描述：IC CPLD 64MC 10NS 100TQFP 集成电路（IC） CPLD（复杂可编程逻辑器件）

封装/外壳：100-TQFP 包装：托盘 描述：IC CPLD 64MC 10NS 100TQFP 集成电路（IC） CPLD（复杂可编程逻辑器件）

可编程逻辑器件(CPLD/FPGA)

30V N-Channel Logic Level PowerTrench BGA MOSFET

General Description Combining Fairchild’s 30V PowerTrench process with state of the art BGA packaging, the FDZ7064N minimizes both PCB space and RDS(ON). This BGA MOSFET embodies a breakthrough in packaging technology which enables the device to combine excellent thermal transfer characteristics,

LOW INPUT OFFSET VOLTAGE C-MOS OPERATIONAL AMPLIFIER???????

文件：163.73 Kbytes Page：4 Pages

LOW INPUT OFFSET VOLTAGE C-MOS OPERATIONAL AMPLIFIER???????

文件：163.73 Kbytes Page：4 Pages

LOW INPUT OFFSET VOLTAGE C-MOS OPERATIONAL AMPLIFIER???????

文件：163.73 Kbytes Page：4 Pages

LOW INPUT OFFSET VOLTAGE C-MOS OPERATIONAL AMPLIFIER???????

文件：163.73 Kbytes Page：4 Pages