Programmable Logic Device Family

General Description The MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counte

Programmable Logic Device Family

General Description The MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counte

Programmable Logic Device Family

General Description The MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counte

Programmable Logic Device Family

General Description The MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counte

Programmable Logic Device Family

General Description The MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counte

Programmable Logic Device Family

General Description The MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counte

封装/外壳：44-LCC（J 形引线） 包装：托盘 描述：IC CPLD 64MC 15NS 44PLCC 集成电路（IC） CPLD（复杂可编程逻辑器件）

封装/外壳：44-LCC（J 形引线） 包装：托盘 描述：IC CPLD 64MC 7.5NS 44PLCC 集成电路（IC） CPLD（复杂可编程逻辑器件）

IC CPLD 64MC 10NS 68PLCC

IC CPLD 64MC 12NS 68PLCC

IC CPLD 64MC 15NS 68PLCC

Synchronous Buck PWM Controller

General Description The APW7064 uses fixed 200kHz switching frequency, voltage mode, synchronous PWM controller which drives dual N-channel MOSFETs. The device integrates the control, monitoring and protection functions into a single package, provides one controlled power output with under-voltag

Synchronous Buck PWM Controller

General Description The APW7064 uses fixed 200kHz switching frequency, voltage mode, synchronous PWM controller which drives dual N-channel MOSFETs. The device integrates the control, monitoring and protection functions into a single package, provides one controlled power output with under-voltag

Male Pins

文件：160.09 Kbytes Page：1 Pages

Inverse DIN 41612 Header

文件：28.59 Kbytes Page：2 Pages