Programmable Logic Device Family

General Description The MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counte

High-performance 3.3-V EEPROM-based programmable logic devices (PLDs) built on second-generation Multiple Array MatriX

General Description MAX 7000A (including MAX 7000AE) devices are high-density, highperformance devices based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROMbased MAX 7000A devices operate with a 3.3-V supply voltage and provide 600 to 10,000 us

Programmable Logic Device

General Description MAX 7000A (including MAX 7000AE) devices are high-density, high-performance devices based on Altera’s second-generation MAX architecture. Features... ■ High-performance 3.3-V EEPROM-based programmable logic devices (PLDs) built on second-generation Multiple Array MatriX

封装/外壳：100-TQFP 包装：托盘 描述：IC CPLD 64MC 10NS 100TQFP 集成电路（IC） CPLD（复杂可编程逻辑器件）

封装/外壳：100-TQFP 包装：托盘 描述：IC CPLD 64MC 4.5NS 100TQFP 集成电路（IC） CPLD（复杂可编程逻辑器件）

CPLD - 复杂可编程逻辑器件 CPLD - MAX 7000 64 Macro 68 IOs

CPLD - 复杂可编程逻辑器件 CPLD - MAX 7000 64 Macro 68 IOs

CPLD - 复杂可编程逻辑器件 CPLD - MAX 7000 64 Macro 36 IOs

Synchronous Buck PWM Controller

General Description The APW7064 uses fixed 200kHz switching frequency, voltage mode, synchronous PWM controller which drives dual N-channel MOSFETs. The device integrates the control, monitoring and protection functions into a single package, provides one controlled power output with under-voltag

Synchronous Buck PWM Controller

General Description The APW7064 uses fixed 200kHz switching frequency, voltage mode, synchronous PWM controller which drives dual N-channel MOSFETs. The device integrates the control, monitoring and protection functions into a single package, provides one controlled power output with under-voltag

Male Pins

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Inverse DIN 41612 Header

文件：28.59 Kbytes Page：2 Pages