14 Pin DIP 5 Tap Low-Profile TTL Compatible Active Delay Lines

14 Pin DIP 5 Tap Low-Profile TTL Compatible Active Delay Lines Whichever is greater. Delay times referenced from input to leading edges at 25°C, 5.0V, with no load

14 Pin DIP 5 Tap Low-Profile TTL Compatible Active Delay Lines

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1:10 Differential LVPECL/LVECL/HSTL Clock and Data Drivers

General Description The MAX9311/MAX9313 are low-skew, 1-to-10 differential drivers designed for clock and data distribution. These devices allow selection between two inputs. The selected input is reproduced at 10 differential outputs. The differential inputs can be adapted to accept single-ended

Line Interface and Line Access Circuit Full-Feature SLIC with High Longitudinal Balance, Ringing Relay,and GR-909 Test Access

文件：852.79 Kbytes Page：50 Pages

Line Interface and Line Access Circuit Full-Feature SLIC with High Longitudinal Balance, Ringing Relay,and GR-909 Test Access

文件：852.79 Kbytes Page：50 Pages

Line Interface and Line Access Circuit Full-Feature SLIC with High Longitudinal Balance, Ringing Relay,and GR-909 Test Access

文件：852.79 Kbytes Page：50 Pages

ENHANCED TT1??SWITCH FABRIC

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