型号 功能描述 生产厂家 企业 LOGO 操作
EP1C6F400

Cyclone FPGA Family

文件:1.14233 Mbytes Page:94 Pages

Altera

阿尔特

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

Section I. Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

Section I. Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

Section I. Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

Section I. Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

Section I. Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

Section I. Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

Cyclone FPGA Family

文件:1.14233 Mbytes Page:94 Pages

Altera

阿尔特

Cyclone FPGA Family

文件:1.14233 Mbytes Page:94 Pages

Altera

阿尔特

Cyclone FPGA Family

文件:1.3576 Mbytes Page:106 Pages

Altera

阿尔特

Cyclone FPGA Family

文件:1.14233 Mbytes Page:94 Pages

Altera

阿尔特

Cyclone FPGA Family

文件:1.14233 Mbytes Page:94 Pages

Altera

阿尔特

Cyclone FPGA Family

文件:1.3576 Mbytes Page:106 Pages

Altera

阿尔特

Cyclone FPGA Family

文件:1.14233 Mbytes Page:94 Pages

Altera

阿尔特

Cyclone FPGA Family

文件:1.14233 Mbytes Page:94 Pages

Altera

阿尔特

Cyclone FPGA Family

文件:1.3576 Mbytes Page:106 Pages

Altera

阿尔特

Cyclone FPGA Family

文件:1.14233 Mbytes Page:94 Pages

Altera

阿尔特

Cyclone FPGA Family

文件:1.14233 Mbytes Page:94 Pages

Altera

阿尔特

Cyclone FPGA Family

文件:1.3576 Mbytes Page:106 Pages

Altera

阿尔特

Cyclone FPGA Family

文件:1.14233 Mbytes Page:94 Pages

Altera

阿尔特

Cyclone FPGA Family

文件:1.14233 Mbytes Page:94 Pages

Altera

阿尔特

Cyclone FPGA Family

文件:1.3576 Mbytes Page:106 Pages

Altera

阿尔特

Cyclone FPGA Family

文件:1.14233 Mbytes Page:94 Pages

Altera

阿尔特

Cyclone FPGA Family

文件:1.14233 Mbytes Page:94 Pages

Altera

阿尔特

Cyclone FPGA Family

文件:1.3576 Mbytes Page:106 Pages

Altera

阿尔特

更新时间:2025-12-27 16:10:00
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
ALTERA
22+
PQFP
2000
全新原装现货!自家库存!
ALTERA
24+
N/A
8000
全新原装正品,现货销售
ALTERA/INTEL
2021
BGA
1000
全新、原装
ALTERA
22+
QFP
20000
公司只有原装 品质保证
ALTERA
23+
QFP
5000
原装正品,假一罚十
ALTERA
18+
QFP
85600
保证进口原装可开17%增值税发票
ALTERA(阿尔特拉)
23+
N/A
4000
公司只做原装,可来电咨询
alte
25+
CDIP
18000
原厂直接发货进口原装
ALTERA
2023+
QFP240
50000
原装现货
ALTERA(阿尔特拉)
25+
封装
500000
源自原厂成本,高价回收工厂呆滞

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