型号 功能描述 生产厂家 企业 LOGO 操作
EP1C3F400

Cyclone FPGA Family

文件:1.14233 Mbytes Page:94 Pages

Altera

阿尔特

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

Section I. Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

Section I. Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

Section I. Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

Section I. Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

Section I. Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

Section I. Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

Cyclone FPGA Family

文件:1.14233 Mbytes Page:94 Pages

Altera

阿尔特

Cyclone FPGA Family

文件:1.14233 Mbytes Page:94 Pages

Altera

阿尔特

Cyclone FPGA Family

文件:1.3576 Mbytes Page:106 Pages

Altera

阿尔特

Cyclone FPGA Family

文件:1.14233 Mbytes Page:94 Pages

Altera

阿尔特

Cyclone FPGA Family

文件:1.3576 Mbytes Page:106 Pages

Altera

阿尔特

Cyclone FPGA Family

文件:1.14233 Mbytes Page:94 Pages

Altera

阿尔特

Cyclone FPGA Family

文件:1.14233 Mbytes Page:94 Pages

Altera

阿尔特

Cyclone FPGA Family

文件:1.14233 Mbytes Page:94 Pages

Altera

阿尔特

Cyclone FPGA Family

文件:1.3576 Mbytes Page:106 Pages

Altera

阿尔特

Cyclone FPGA Family

文件:1.14233 Mbytes Page:94 Pages

Altera

阿尔特

Cyclone FPGA Family

文件:1.14233 Mbytes Page:94 Pages

Altera

阿尔特

Cyclone FPGA Family

文件:1.3576 Mbytes Page:106 Pages

Altera

阿尔特

Cyclone FPGA Family

文件:1.14233 Mbytes Page:94 Pages

Altera

阿尔特

Cyclone FPGA Family

文件:1.14233 Mbytes Page:94 Pages

Altera

阿尔特

Cyclone FPGA Family

文件:1.3576 Mbytes Page:106 Pages

Altera

阿尔特

Cyclone FPGA Family

文件:1.14233 Mbytes Page:94 Pages

Altera

阿尔特

Cyclone FPGA Family

文件:1.14233 Mbytes Page:94 Pages

Altera

阿尔特

Cyclone FPGA Family

文件:1.3576 Mbytes Page:106 Pages

Altera

阿尔特

EP1C3F400产品属性

  • 类型

    描述

  • 型号

    EP1C3F400

  • 制造商

    ALTERA

  • 制造商全称

    Altera Corporation

  • 功能描述

    Cyclone FPGA Family

更新时间:2025-11-5 13:48:00
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
ALTERA/阿尔特拉
25+
QFP
996880
只做原装,欢迎来电资询
ALTERA(阿尔特拉)
24+
32000
全新原厂原装正品现货,低价出售,实单可谈
ALTERA(阿尔特拉)
24+
N/A
4000
十年沉淀唯有原装
ALTERA/阿尔特拉
24+
NA/
3280
原装现货,当天可交货,原型号开票
TQFP
5
ALTERA(阿尔特拉)
24+
N/A
4000
原厂原装,价格优势,欢迎洽谈!
ALTERA
2138+
QFP
8960
专营BGA,QFP原装现货,假一赔十
ALTERA(阿尔特拉)
2511
N/A
4000
电子元器件采购降本30%!原厂直采,砍掉中间差价
ALTERA
QFP
1000
正品原装--自家现货-实单可谈
ALTERA(阿尔特拉)
25+
N/A
4000
原装,请咨询

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