丝印代码：EA32882B；28-Bit to 56-Bit Registered Buffer With Address Parity Test One Pair to Four Pair Differential Clock PLL Driver

1FEATURES • JEDEC SSTE32882 Compliant • 1-to-2 Register Outputs and 1-to-4 Clock Pair Outputs Support Stacked DDR3 RDIMMs • CKE Powerdown Mode for Optimized System Power Consumption • 1.5V/1.35V Phase Lock Loop Clock Driver for Buffering One Differential Clock Pair (CK and CK) and Distribu

丝印代码：EA32882B；28-Bit to 56-Bit Registered Buffer With Address Parity Test One Pair to Four Pair Differential Clock PLL Driver

1FEATURES • JEDEC SSTE32882 Compliant • 1-to-2 Register Outputs and 1-to-4 Clock Pair Outputs Support Stacked DDR3 RDIMMs • CKE Powerdown Mode for Optimized System Power Consumption • 1.5V/1.35V Phase Lock Loop Clock Driver for Buffering One Differential Clock Pair (CK and CK) and Distribu

TERMINAL, RING TOMGUE, BUDGET

文件：82.56 Kbytes Page：1 Pages

1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT

文件：1.37611 Mbytes Page：73 Pages

Pinout optimizes DDR3 RDIMM PCB layout

文件：1.37612 Mbytes Page：73 Pages