Features

ÎÎ One LVCMOS/LVTTL output

ÎÎ Differential CLK/nCLK input pair

ÎÎ CLK/nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL

ÎÎ Output frequency: 360MHz

ÎÎ Additive phase jitter, RMS: 0.09ps (typical), 3.3V output

ÎÎ Full 3.3V and 2.5V operating supply

ÎÎ -40°C to 105°C ambient operating temperature

ÎÎ Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2)

ÎÎ Halogen and Antimony Free. “Green” Device (Note 3)

ÎÎ For automotive applications requiring specific change control (i.e. parts qualified to AEC-Q100/101/200, PPAP capable, and manufactured in IATF 16949 certified facilities), please contact us or your local Diodes representative. https://www.diodes.com/quality/product-definitions/

ÎÎ Packaging (Pb-free & Green): Small 8-pin SOIC(W) package saves board space

Description

The PI6C49CB01J is a industrial grade 1-to-1 Differential-to-LVCMOS/LVTTL Translator High Performance Buffer. The differential input is highly flexible and can accept LVPECL, LVDS, LVHSTL, SSTL, and HCSL. The small 8-lead SOIC footprint makes this device ideal for use in applications with limited board space.

Application Information

Wiring the differential input to accept single ended levels Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to postion the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R1/R2 = 0.609.