丝印代码：TL；100mA / 50V Digital transistors

Features 1) Built-In Biasing Resistors, R1 = 10kΩ, R2 = 47kΩ. 2) Built-in bias resistors enable the configuration of an inverter circuit without connecting external input resistors (see inner circuit) . 3) Only the on/off conditions need to be set for operation, making the circuit d

丝印代码：64；NPN 100mA 50V Digital Transistors (Bias Resistor Built-in Transistors)

Features 1) Built-in bias resistors enable the configuration of an inverter circuit without connecting external input resistors (see equivalent circuit). 2) The bias resistors consist of thin-film resistors with complete isolation to allow negative biasing of the input. They also

丝印代码：64；NPN 100mA 50V Digital Transistors

Features 1) Built-in bias resistors enable the configuration of an inverter circuit without connecting external input resistors (see equivalent circuit). 2) The bias resistors consist of thin-film resistors with complete isolation to allow negative biasing of the input. They also

Digital transistor(with built-in resistors)

罗姆开发了数字晶体管的标准产品。 • Built-In Biasing Resistors, R1 = 10kΩ, R2 = 47kΩ\n• Built-in bias resistors enable the configuration of an inverter circuit without connecting external input resistors (see inner circuit) .\n• Only the on/off conditions need to be set for operation, making the circuit design easy.\n• Complementary;

丝印代码：64；NPN 100mA 50V Digital Transistor

文件：1.99099 Mbytes Page：13 Pages

NPN 100mA 50V Digital Transistor

文件：1.99444 Mbytes Page：12 Pages

NPN 100mA 50V Digital Transistors (Bias Resistor Built-in Transistors)

1) Built-In Biasing Resistors\n2) Built-in bias resistors enable the configuration of\n   an inverter circuit without connecting external input resistors (see inner circuit).\n3) The bias resistors consist of thin-film resistors with complete isolation to allow negative biasing\n   of the input. The;

PNP 数字晶体管(电阻内置型晶体管)（AEC-Q101标准）

DTC114YEBHZG是高可靠性车载用数字晶体管(电阻内置型晶体管。 • Built-In Biasing Resistors, R1 = 10kΩ, R2 = 47kΩ\n• Built-in bias resistors enable the configuration of an inverter circuit without connecting external input resistors (see inner circuit).\n• Only the on/off conditions need to be set for operation, making the circuit design easy.\n• Complementary ;

NPN 100mA 50V Digital Transistor (Bias Resistor Built-in Transistor)

文件：1.05636 Mbytes Page：8 Pages

封装/外壳：SC-89，SOT-490 包装：剪切带（CT）Digi-Reel® 得捷定制卷带 描述：TRANS NPN 100MA 50V SOT-416FL 分立半导体产品 晶体管 - 双极（BJT）- 单，预偏置

封装/外壳：SC-89，SOT-490 包装：卷带（TR） 描述：TRANS PREBIAS NPN 150MW EMT3F 分立半导体产品 晶体管 - 双极（BJT）- 单，预偏置

CASE 463-01, STYLE 1 SOT-416/SC-90

The BRT (Bias Resistor Transistor) contains a single transistor with a monolithic bias network consisting of two resistors; a series base resistor and a base–emitter resistor. These digital transistors are designed to replace a single device and its external resistor bias network. The BRT eliminat

CASE 463-01, STYLE 1 SOT-416/SC-90

Bias Resistor Transistor NPN Silicon Surface Mount Transistor with Monolithic Bias Resistor Network The BRT (Bias Resistor Transistor) contains a single transistor with a monolithic bias network consisting of two resistors; a series base resistor and a base–emitter resistor. These digital trans

PNP SILICON BIAS RESISTOR TRANSISTOR

This new series of digital transistors is designed to replace a single device and its external resistor bias network. The BRT (Bias Resistor Transistor) contains a single transistor with a monolithic bias network consisting of two resistors; a series base resistor and a base–emitter resistor. The

Bias Resistor Transistor PNP Silicon Surface Mount Transistor with Monolithic Bias Resistor Network

The BRT (Bias Resistor Transistor) contains a single transistor with a monolithic bias network consisting of two resistors; a series base resistor and a base–emitter resistor. These digital transistors are designed to replace a single device and its xternal resistor bias network. The BRT eliminate

0.25關m Sea of Gates and Customer Structured Arrays

DESCRIPTION Oki’s 0.25µm Application-Specific Integrated Circuit (ASIC) products are available in both Sea Of Gates (SOG) and Customer Structured Array (CSA) architectures. Both the SOG-based MG115P series and the CSA-based MG75P series use a five-layer metal process on 0.25µm drawn (0.18µm L-eff