DS90LV032A 3V LVDS Quad CMOS Differential Line Receiver

文件：975.32 Kbytes Page：18 Pages

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 包装：管件 描述：IC RECEIVER 0/4 16SOIC 集成电路（IC） 驱动器，接收器，收发器

DS90LV032A 3-V LVDS Quad CMOS Differential Line Receiver

1 Features 1• >400 Mbps (200 MHz) Switching Rates • 0.1-ns Channel-to-Channel Skew (Typical) • 0.1-ns Differential Skew (Typical) • 3.3-ns Maximum Propagation Delay • 3.3-V Power Supply Design • Power Down High Impedance on LVDS Inputs • Low Power Design (40 mW at 3.3 V Static) • Interoper

DS90LV032A 3-V LVDS Quad CMOS Differential Line Receiver

1 Features 1• >400 Mbps (200 MHz) Switching Rates • 0.1-ns Channel-to-Channel Skew (Typical) • 0.1-ns Differential Skew (Typical) • 3.3-ns Maximum Propagation Delay • 3.3-V Power Supply Design • Power Down High Impedance on LVDS Inputs • Low Power Design (40 mW at 3.3 V Static) • Interoper

DS90LV032A 3-V LVDS Quad CMOS Differential Line Receiver

1 Features 1• >400 Mbps (200 MHz) Switching Rates • 0.1-ns Channel-to-Channel Skew (Typical) • 0.1-ns Differential Skew (Typical) • 3.3-ns Maximum Propagation Delay • 3.3-V Power Supply Design • Power Down High Impedance on LVDS Inputs • Low Power Design (40 mW at 3.3 V Static) • Interoper

DS90LV032A 3-V LVDS Quad CMOS Differential Line Receiver

1 Features 1• >400 Mbps (200 MHz) Switching Rates • 0.1-ns Channel-to-Channel Skew (Typical) • 0.1-ns Differential Skew (Typical) • 3.3-ns Maximum Propagation Delay • 3.3-V Power Supply Design • Power Down High Impedance on LVDS Inputs • Low Power Design (40 mW at 3.3 V Static) • Interoper

DS90LV032A 3V LVDS Quad CMOS Differential Line Receiver

文件：975.32 Kbytes Page：18 Pages

DS90LV032A 3V LVDS Quad CMOS Differential Line Receiver

文件：975.32 Kbytes Page：18 Pages

DS90LV032A 3-V LVDS Quad CMOS Differential Line Receiver

1 Features 1• >400 Mbps (200 MHz) Switching Rates • 0.1-ns Channel-to-Channel Skew (Typical) • 0.1-ns Differential Skew (Typical) • 3.3-ns Maximum Propagation Delay • 3.3-V Power Supply Design • Power Down High Impedance on LVDS Inputs • Low Power Design (40 mW at 3.3 V Static) • Interoper

3V LVDS Quad CMOS Differential Line Receiver

文件：192.95 Kbytes Page：9 Pages

3V LVDS Quad CMOS Differential Line Receiver

文件：457.49 Kbytes Page：16 Pages

DS90LV032AQML 3V LVDS Quad CMOS Differential Line Receiver

文件：269.99 Kbytes Page：14 Pages

3V LVDS Quad CMOS Differential Line Receiver

文件：457.49 Kbytes Page：16 Pages