DS90LV032A 3-V LVDS Quad CMOS Differential Line Receiver

1 Features 1• >400 Mbps (200 MHz) Switching Rates • 0.1-ns Channel-to-Channel Skew (Typical) • 0.1-ns Differential Skew (Typical) • 3.3-ns Maximum Propagation Delay • 3.3-V Power Supply Design • Power Down High Impedance on LVDS Inputs • Low Power Design (40 mW at 3.3 V Static) • Interoper

3V 400Mbps LVDS 四路差动线路接收器

The DS90LV032A is a quad CMOS differential line receiver designed for applications requiring ultra-low power dissipation and high data rates. The device is designed to support data rates in excess of 400 Mbps (200 MHz) using Low Voltage Differential Signaling (LVDS) technology.The DS90LV032A accepts • >400 Mbps (200 MHz) Switching Rates\n• 0.1-ns Channel-to-Channel Skew (Typical)\n• 0.1-ns Differential Skew (Typical)\n• 3.3-ns Maximum Propagation Delay\n• 3.3-V Power Supply Design\n• Power Down High Impedance on LVDS Inputs\n• Low Power Design (40 mW at 3.3 V Static)\n• Interoperable With Exist;

3V LVDS Quad CMOS Differential Line Receiver

文件：192.95 Kbytes Page：9 Pages

丝印代码：DS90LV032ATM；DS90LV032A 3-V LVDS Quad CMOS Differential Line Receiver

1 Features 1• >400 Mbps (200 MHz) Switching Rates • 0.1-ns Channel-to-Channel Skew (Typical) • 0.1-ns Differential Skew (Typical) • 3.3-ns Maximum Propagation Delay • 3.3-V Power Supply Design • Power Down High Impedance on LVDS Inputs • Low Power Design (40 mW at 3.3 V Static) • Interoper

丝印代码：DS90LV032ATM；DS90LV032A 3-V LVDS Quad CMOS Differential Line Receiver

1 Features 1• >400 Mbps (200 MHz) Switching Rates • 0.1-ns Channel-to-Channel Skew (Typical) • 0.1-ns Differential Skew (Typical) • 3.3-ns Maximum Propagation Delay • 3.3-V Power Supply Design • Power Down High Impedance on LVDS Inputs • Low Power Design (40 mW at 3.3 V Static) • Interoper

丝印代码：DS90LV032ATM；DS90LV032A 3-V LVDS Quad CMOS Differential Line Receiver

1 Features 1• >400 Mbps (200 MHz) Switching Rates • 0.1-ns Channel-to-Channel Skew (Typical) • 0.1-ns Differential Skew (Typical) • 3.3-ns Maximum Propagation Delay • 3.3-V Power Supply Design • Power Down High Impedance on LVDS Inputs • Low Power Design (40 mW at 3.3 V Static) • Interoper

丝印代码：DS90LV032ATM；DS90LV032A 3-V LVDS Quad CMOS Differential Line Receiver

1 Features 1• >400 Mbps (200 MHz) Switching Rates • 0.1-ns Channel-to-Channel Skew (Typical) • 0.1-ns Differential Skew (Typical) • 3.3-ns Maximum Propagation Delay • 3.3-V Power Supply Design • Power Down High Impedance on LVDS Inputs • Low Power Design (40 mW at 3.3 V Static) • Interoper

丝印代码：DS90LV032AT；DS90LV032A 3-V LVDS Quad CMOS Differential Line Receiver

1 Features 1• >400 Mbps (200 MHz) Switching Rates • 0.1-ns Channel-to-Channel Skew (Typical) • 0.1-ns Differential Skew (Typical) • 3.3-ns Maximum Propagation Delay • 3.3-V Power Supply Design • Power Down High Impedance on LVDS Inputs • Low Power Design (40 mW at 3.3 V Static) • Interoper

丝印代码：DS90LV032AT；DS90LV032A 3-V LVDS Quad CMOS Differential Line Receiver

1 Features 1• >400 Mbps (200 MHz) Switching Rates • 0.1-ns Channel-to-Channel Skew (Typical) • 0.1-ns Differential Skew (Typical) • 3.3-ns Maximum Propagation Delay • 3.3-V Power Supply Design • Power Down High Impedance on LVDS Inputs • Low Power Design (40 mW at 3.3 V Static) • Interoper

丝印代码：DS90LV032AT；DS90LV032A 3-V LVDS Quad CMOS Differential Line Receiver

1 Features 1• >400 Mbps (200 MHz) Switching Rates • 0.1-ns Channel-to-Channel Skew (Typical) • 0.1-ns Differential Skew (Typical) • 3.3-ns Maximum Propagation Delay • 3.3-V Power Supply Design • Power Down High Impedance on LVDS Inputs • Low Power Design (40 mW at 3.3 V Static) • Interoper

丝印代码：DS90LV032AT；DS90LV032A 3-V LVDS Quad CMOS Differential Line Receiver

1 Features 1• >400 Mbps (200 MHz) Switching Rates • 0.1-ns Channel-to-Channel Skew (Typical) • 0.1-ns Differential Skew (Typical) • 3.3-ns Maximum Propagation Delay • 3.3-V Power Supply Design • Power Down High Impedance on LVDS Inputs • Low Power Design (40 mW at 3.3 V Static) • Interoper

丝印代码：DS90LV032ATM；DS90LV032A 3-V LVDS Quad CMOS Differential Line Receiver

1 Features 1• >400 Mbps (200 MHz) Switching Rates • 0.1-ns Channel-to-Channel Skew (Typical) • 0.1-ns Differential Skew (Typical) • 3.3-ns Maximum Propagation Delay • 3.3-V Power Supply Design • Power Down High Impedance on LVDS Inputs • Low Power Design (40 mW at 3.3 V Static) • Interoper

丝印代码：DS90LV032ATM；DS90LV032A 3-V LVDS Quad CMOS Differential Line Receiver

1 Features 1• >400 Mbps (200 MHz) Switching Rates • 0.1-ns Channel-to-Channel Skew (Typical) • 0.1-ns Differential Skew (Typical) • 3.3-ns Maximum Propagation Delay • 3.3-V Power Supply Design • Power Down High Impedance on LVDS Inputs • Low Power Design (40 mW at 3.3 V Static) • Interoper

丝印代码：DS90LV032ATM；DS90LV032A 3-V LVDS Quad CMOS Differential Line Receiver

1 Features 1• >400 Mbps (200 MHz) Switching Rates • 0.1-ns Channel-to-Channel Skew (Typical) • 0.1-ns Differential Skew (Typical) • 3.3-ns Maximum Propagation Delay • 3.3-V Power Supply Design • Power Down High Impedance on LVDS Inputs • Low Power Design (40 mW at 3.3 V Static) • Interoper

丝印代码：DS90LV032ATM；DS90LV032A 3-V LVDS Quad CMOS Differential Line Receiver

1 Features 1• >400 Mbps (200 MHz) Switching Rates • 0.1-ns Channel-to-Channel Skew (Typical) • 0.1-ns Differential Skew (Typical) • 3.3-ns Maximum Propagation Delay • 3.3-V Power Supply Design • Power Down High Impedance on LVDS Inputs • Low Power Design (40 mW at 3.3 V Static) • Interoper

3V LVDS 四路 CMOS 差动线路接收器

The DS90LV032A is a quad CMOS differential line receiver designed for applications requiring ultra low power dissipation and high data rates. The DS90LV032A accepts low voltage (350 mV typical) differential input signals and translates them to 3V CMOS output levels. The receiver supports a TRI-STATE • Low chip to chip skew\n• Low differential skew\n• High impedance LVDS inputs with power-off\n• Low power dissipation\n• Accepts small swing (330 mV) differential signal levels.\n• Compatible with ANSI/TIA/EIA-644\n• Operating temperature range (-55°C to +85°C)\n• Pin compatible with DS90C032A and ;

3V LVDS 四路 CMOS 差动线路接收器

The DS90LV032A is a quad CMOS differential line receiver designed for applications requiring ultra low power dissipation and high data rates. The DS90LV032A accepts low voltage (350 mV typical) differential input signals and translates them to 3V CMOS output levels. The receiver supports a TRI-STATE • Low chip to chip skew\n• Low differential skew\n• High impedance LVDS inputs with power-off\n• Low power dissipation\n• Accepts small swing (330 mV) differential signal levels.\n• Compatible with ANSI/TIA/EIA-644\n• Operating temperature range (-55°C to +85°C)\n• Pin compatible with DS90C032A and ;

3V LVDS Quad CMOS Differential Line Receiver

文件：457.49 Kbytes Page：16 Pages

DS90LV032AQML 3V LVDS Quad CMOS Differential Line Receiver

文件：269.99 Kbytes Page：14 Pages

3V LVDS Quad CMOS Differential Line Receiver

文件：457.49 Kbytes Page：16 Pages

3V LVDS Quad CMOS Differential Line Receiver

文件：457.49 Kbytes Page：16 Pages

DS90LV032A 3V LVDS Quad CMOS Differential Line Receiver

文件：975.32 Kbytes Page：18 Pages

3V LVDS Quad CMOS Differential Line Receiver

文件：192.95 Kbytes Page：9 Pages

DS90LV032A 3V LVDS Quad CMOS Differential Line Receiver

文件：975.32 Kbytes Page：18 Pages

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC RECEIVER 0/4 16SOIC 集成电路（IC） 驱动器，接收器，收发器

DS90LV032A 3V LVDS Quad CMOS Differential Line Receiver

文件：975.32 Kbytes Page：18 Pages

DS90LV032A 3V LVDS Quad CMOS Differential Line Receiver

文件：975.32 Kbytes Page：18 Pages

3V LVDS Quad CMOS Differential Line Receiver

文件：192.95 Kbytes Page：9 Pages

封装/外壳：16-TSSOP（0.173"，4.40mm 宽） 包装：管件 描述：IC RECEIVER 0/4 16TSSOP 集成电路（IC） 驱动器，接收器，收发器

DS90LV032A 3V LVDS Quad CMOS Differential Line Receiver

文件：975.32 Kbytes Page：18 Pages

DS90LV032A 3V LVDS Quad CMOS Differential Line Receiver

文件：975.32 Kbytes Page：18 Pages

DS90LV032A 3V LVDS Quad CMOS Differential Line Receiver

文件：975.32 Kbytes Page：18 Pages

DS90LV032A 3V LVDS Quad CMOS Differential Line Receiver

文件：975.32 Kbytes Page：18 Pages

DS90LV032A 3V LVDS Quad CMOS Differential Line Receiver

文件：975.32 Kbytes Page：18 Pages

DS90LV032A 3V LVDS Quad CMOS Differential Line Receiver

文件：975.32 Kbytes Page：18 Pages

DS90LV032A 3V LVDS Quad CMOS Differential Line Receiver

文件：975.32 Kbytes Page：18 Pages

DS90LV032A 3V LVDS Quad CMOS Differential Line Receiver

文件：975.32 Kbytes Page：18 Pages

DS90LV032AQML 3V LVDS Quad CMOS Differential Line Receiver

文件：269.99 Kbytes Page：14 Pages

DS90LV032AQML 3V LVDS Quad CMOS Differential Line Receiver

文件：433.21 Kbytes Page：16 Pages

3V LVDS Quad CMOS Differential Line Receiver

文件：457.49 Kbytes Page：16 Pages

DS90LV032AQML 3V LVDS Quad CMOS Differential Line Receiver

文件：269.99 Kbytes Page：14 Pages

3V LVDS Quad CMOS Differential Line Receiver

文件：457.49 Kbytes Page：16 Pages

DS90LV032AQML 3V LVDS Quad CMOS Differential Line Receiver

文件：433.21 Kbytes Page：16 Pages

DS90LV032AQML 3V LVDS Quad CMOS Differential Line Receiver

文件：269.99 Kbytes Page：14 Pages

DS90LV032AQML 3V LVDS Quad CMOS Differential Line Receiver

文件：433.21 Kbytes Page：16 Pages

DS90LV032AQML 3V LVDS Quad CMOS Differential Line Receiver

文件：269.99 Kbytes Page：14 Pages

3V LVDS Quad CMOS Differential Line Receiver

文件：457.49 Kbytes Page：16 Pages

3V LVDS High-Speed Differential Line Drivers

Description The PI90LV031A, PI90LV027A, and PI90LV017A are differential line drivers that use low-voltage differential signaling (LVDS) to support data rates in excess of 400 Mbps. These products are designed for applications requiring high-speed, low-power consumption and low noise generation.

3V LVDS High-Speed Differential Line Receivers

Description The PI90LV032A, PI90LV028A, and PI90LV018A are differential line receivers that use low-voltage differential signaling (LVDS) to support data rates in excess of 400 Mbps. These products are designed for applications requiring high-speed, low-power consumption and low noise generation.