DS90CF384A/DS90CF364A 3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link - 65 MHz, 3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link - 65 MHz

1FEATURES 2• 20 to 65 MHz Shift Clock Support • 50% Duty Cycle on Receiver Output Clock • Best-in-Class Set & Hold Times on RxOUTPUTs • Rx Power Consumption 7 kV (HBM), >700V (EIAJ) • Supports VGA, SVGA, XG

3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link - 65MHz

文件：1.44803 Mbytes Page：22 Pages

封装/外壳：56-TFSOP（0.240"，6.10mm 宽） 包装：管件 描述：IC INTERFACE SPECIALIZED 56TSSOP 集成电路（IC） 专用

DS90C383/DS90CF384 3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz, 3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65 MHz

General Description The DS90C383 transmitter converts 28 bits of LVCMOS/ LVTTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bit

3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz, 3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65 MHz

文件：344.12 Kbytes Page：20 Pages

3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz

文件：410.45 Kbytes Page：22 Pages

DS90CF384A/DS90CF364A 3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link - 65 MHz, 3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link - 65 MHz

1FEATURES 2• 20 to 65 MHz Shift Clock Support • 50% Duty Cycle on Receiver Output Clock • Best-in-Class Set & Hold Times on RxOUTPUTs • Rx Power Consumption 7 kV (HBM), >700V (EIAJ) • Supports VGA, SVGA, XG

3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65 MHz, 3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link-65 MHz

文件：784.1 Kbytes Page：16 Pages

3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65MHz, 3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link-65MHz

文件：439.56 Kbytes Page：18 Pages