丝印代码：DS25BR400TSQ；DS25BR400 Quad 2.5 Gbps CML Transceiver with Transmit De-Emphasis and Receive Equalization

1FEATURES 2• 250 Mbps – 2.5 Gbps Low Jitter Operation • Optional Fixed Input Equalization • Selectable Output De-Emphasis • Individual Loopback Controls • On-Chip Termination • +3.3V Supply • Lead-Less WQFN-60 Pin Package – (9 mm x9 mm x0.8 mm, 0.5 mm Pitch) • −40°C to +85°C Industrial Te

丝印代码：DS25BR400TSQ；DS25BR400 Quad 2.5 Gbps CML Transceiver with Transmit De-Emphasis and Receive Equalization

1FEATURES 2• 250 Mbps – 2.5 Gbps Low Jitter Operation • Optional Fixed Input Equalization • Selectable Output De-Emphasis • Individual Loopback Controls • On-Chip Termination • +3.3V Supply • Lead-Less WQFN-60 Pin Package – (9 mm x9 mm x0.8 mm, 0.5 mm Pitch) • −40°C to +85°C Industrial Te

丝印代码：DS25BR400TSQ；DS25BR400 Quad 2.5 Gbps CML Transceiver with Transmit De-Emphasis and Receive Equalization

1FEATURES 2• 250 Mbps – 2.5 Gbps Low Jitter Operation • Optional Fixed Input Equalization • Selectable Output De-Emphasis • Individual Loopback Controls • On-Chip Termination • +3.3V Supply • Lead-Less WQFN-60 Pin Package – (9 mm x9 mm x0.8 mm, 0.5 mm Pitch) • −40°C to +85°C Industrial Te

丝印代码：DS25BR400TSQ；DS25BR400 Quad 2.5 Gbps CML Transceiver with Transmit De-Emphasis and Receive Equalization

1FEATURES 2• 250 Mbps – 2.5 Gbps Low Jitter Operation • Optional Fixed Input Equalization • Selectable Output De-Emphasis • Individual Loopback Controls • On-Chip Termination • +3.3V Supply • Lead-Less WQFN-60 Pin Package – (9 mm x9 mm x0.8 mm, 0.5 mm Pitch) • −40°C to +85°C Industrial Te

DS25BR100 / DS25BR101 3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization

1FEATURES 2• DC - 3.125 Gbps Low Jitter, High Noise Immunity, Low Power Operation • Receive Equalization Reduces ISI Jitter Due to Media Loss • Transmit Pre-Emphasis Drives Lossy Backplanes and Cables • On-Chip 100Ω Input and Output Termination: – Minimizes Insertion and Return Losses – R

丝印代码：2R100；DS25BR100 / DS25BR101 3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization

1FEATURES 2• DC - 3.125 Gbps Low Jitter, High Noise Immunity, Low Power Operation • Receive Equalization Reduces ISI Jitter Due to Media Loss • Transmit Pre-Emphasis Drives Lossy Backplanes and Cables • On-Chip 100Ω Input and Output Termination: – Minimizes Insertion and Return Losses – R

丝印代码：2R100；DS25BR100 / DS25BR101 3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization

1FEATURES 2• DC - 3.125 Gbps Low Jitter, High Noise Immunity, Low Power Operation • Receive Equalization Reduces ISI Jitter Due to Media Loss • Transmit Pre-Emphasis Drives Lossy Backplanes and Cables • On-Chip 100Ω Input and Output Termination: – Minimizes Insertion and Return Losses – R

丝印代码：2R100；DS25BR100 / DS25BR101 3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization

1FEATURES 2• DC - 3.125 Gbps Low Jitter, High Noise Immunity, Low Power Operation • Receive Equalization Reduces ISI Jitter Due to Media Loss • Transmit Pre-Emphasis Drives Lossy Backplanes and Cables • On-Chip 100Ω Input and Output Termination: – Minimizes Insertion and Return Losses – R

丝印代码：2R100；DS25BR100 / DS25BR101 3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization

1FEATURES 2• DC - 3.125 Gbps Low Jitter, High Noise Immunity, Low Power Operation • Receive Equalization Reduces ISI Jitter Due to Media Loss • Transmit Pre-Emphasis Drives Lossy Backplanes and Cables • On-Chip 100Ω Input and Output Termination: – Minimizes Insertion and Return Losses – R

DS25BR100 / DS25BR101 3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization

1FEATURES 2• DC - 3.125 Gbps Low Jitter, High Noise Immunity, Low Power Operation • Receive Equalization Reduces ISI Jitter Due to Media Loss • Transmit Pre-Emphasis Drives Lossy Backplanes and Cables • On-Chip 100Ω Input and Output Termination: – Minimizes Insertion and Return Losses – R

丝印代码：2R101；DS25BR100 / DS25BR101 3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization

1FEATURES 2• DC - 3.125 Gbps Low Jitter, High Noise Immunity, Low Power Operation • Receive Equalization Reduces ISI Jitter Due to Media Loss • Transmit Pre-Emphasis Drives Lossy Backplanes and Cables • On-Chip 100Ω Input and Output Termination: – Minimizes Insertion and Return Losses – R

丝印代码：2R101；DS25BR100 / DS25BR101 3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization

1FEATURES 2• DC - 3.125 Gbps Low Jitter, High Noise Immunity, Low Power Operation • Receive Equalization Reduces ISI Jitter Due to Media Loss • Transmit Pre-Emphasis Drives Lossy Backplanes and Cables • On-Chip 100Ω Input and Output Termination: – Minimizes Insertion and Return Losses – R

丝印代码：2R101；DS25BR100 / DS25BR101 3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization

1FEATURES 2• DC - 3.125 Gbps Low Jitter, High Noise Immunity, Low Power Operation • Receive Equalization Reduces ISI Jitter Due to Media Loss • Transmit Pre-Emphasis Drives Lossy Backplanes and Cables • On-Chip 100Ω Input and Output Termination: – Minimizes Insertion and Return Losses – R

丝印代码：2R101；DS25BR100 / DS25BR101 3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization

1FEATURES 2• DC - 3.125 Gbps Low Jitter, High Noise Immunity, Low Power Operation • Receive Equalization Reduces ISI Jitter Due to Media Loss • Transmit Pre-Emphasis Drives Lossy Backplanes and Cables • On-Chip 100Ω Input and Output Termination: – Minimizes Insertion and Return Losses – R

丝印代码：2R101；DS25BR100 / DS25BR101 3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization

1FEATURES 2• DC - 3.125 Gbps Low Jitter, High Noise Immunity, Low Power Operation • Receive Equalization Reduces ISI Jitter Due to Media Loss • Transmit Pre-Emphasis Drives Lossy Backplanes and Cables • On-Chip 100Ω Input and Output Termination: – Minimizes Insertion and Return Losses – R

丝印代码：2R101；DS25BR100 / DS25BR101 3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization

1FEATURES 2• DC - 3.125 Gbps Low Jitter, High Noise Immunity, Low Power Operation • Receive Equalization Reduces ISI Jitter Due to Media Loss • Transmit Pre-Emphasis Drives Lossy Backplanes and Cables • On-Chip 100Ω Input and Output Termination: – Minimizes Insertion and Return Losses – R

丝印代码：2R101；DS25BR100 / DS25BR101 3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization

1FEATURES 2• DC - 3.125 Gbps Low Jitter, High Noise Immunity, Low Power Operation • Receive Equalization Reduces ISI Jitter Due to Media Loss • Transmit Pre-Emphasis Drives Lossy Backplanes and Cables • On-Chip 100Ω Input and Output Termination: – Minimizes Insertion and Return Losses – R

丝印代码：2R101；DS25BR100 / DS25BR101 3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization

1FEATURES 2• DC - 3.125 Gbps Low Jitter, High Noise Immunity, Low Power Operation • Receive Equalization Reduces ISI Jitter Due to Media Loss • Transmit Pre-Emphasis Drives Lossy Backplanes and Cables • On-Chip 100Ω Input and Output Termination: – Minimizes Insertion and Return Losses – R

丝印代码：2R101；DS25BR100 / DS25BR101 3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization

1FEATURES 2• DC - 3.125 Gbps Low Jitter, High Noise Immunity, Low Power Operation • Receive Equalization Reduces ISI Jitter Due to Media Loss • Transmit Pre-Emphasis Drives Lossy Backplanes and Cables • On-Chip 100Ω Input and Output Termination: – Minimizes Insertion and Return Losses – R

丝印代码：2R101；DS25BR100 / DS25BR101 3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization

1FEATURES 2• DC - 3.125 Gbps Low Jitter, High Noise Immunity, Low Power Operation • Receive Equalization Reduces ISI Jitter Due to Media Loss • Transmit Pre-Emphasis Drives Lossy Backplanes and Cables • On-Chip 100Ω Input and Output Termination: – Minimizes Insertion and Return Losses – R

丝印代码：2R101；DS25BR100 / DS25BR101 3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization

1FEATURES 2• DC - 3.125 Gbps Low Jitter, High Noise Immunity, Low Power Operation • Receive Equalization Reduces ISI Jitter Due to Media Loss • Transmit Pre-Emphasis Drives Lossy Backplanes and Cables • On-Chip 100Ω Input and Output Termination: – Minimizes Insertion and Return Losses – R

丝印代码：2R101；DS25BR100 / DS25BR101 3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization

1FEATURES 2• DC - 3.125 Gbps Low Jitter, High Noise Immunity, Low Power Operation • Receive Equalization Reduces ISI Jitter Due to Media Loss • Transmit Pre-Emphasis Drives Lossy Backplanes and Cables • On-Chip 100Ω Input and Output Termination: – Minimizes Insertion and Return Losses – R

DS25BR110 3.125 Gbps LVDS Buffer with Receive Equalization

1FEATURES 2• DC - 3.125 Gbps Low Jitter, High Noise Immunity, Low Power Operation • Four Levels of Receive Equalization Reduce ISI Jitter • On-Chip 100Ω Input and Output Termination Minimizes Insertion and Return Losses, Reduces Component Count, and Minimizes Board Space • 7 kV ESD on LVD

DS25BR100 / DS25BR101 3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization

1FEATURES 2• DC - 3.125 Gbps Low Jitter, High Noise Immunity, Low Power Operation • Receive Equalization Reduces ISI Jitter Due to Media Loss • Transmit Pre-Emphasis Drives Lossy Backplanes and Cables • On-Chip 100Ω Input and Output Termination: – Minimizes Insertion and Return Losses – R

丝印代码：2R110；DS25BR110 3.125 Gbps LVDS Buffer with Receive Equalization

1FEATURES 2• DC - 3.125 Gbps Low Jitter, High Noise Immunity, Low Power Operation • Four Levels of Receive Equalization Reduce ISI Jitter • On-Chip 100Ω Input and Output Termination Minimizes Insertion and Return Losses, Reduces Component Count, and Minimizes Board Space • 7 kV ESD on LVD

丝印代码：2R110；DS25BR110 3.125 Gbps LVDS Buffer with Receive Equalization

1FEATURES 2• DC - 3.125 Gbps Low Jitter, High Noise Immunity, Low Power Operation • Four Levels of Receive Equalization Reduce ISI Jitter • On-Chip 100Ω Input and Output Termination Minimizes Insertion and Return Losses, Reduces Component Count, and Minimizes Board Space • 7 kV ESD on LVD

丝印代码：2R110；DS25BR110 3.125 Gbps LVDS Buffer with Receive Equalization

1FEATURES 2• DC - 3.125 Gbps Low Jitter, High Noise Immunity, Low Power Operation • Four Levels of Receive Equalization Reduce ISI Jitter • On-Chip 100Ω Input and Output Termination Minimizes Insertion and Return Losses, Reduces Component Count, and Minimizes Board Space • 7 kV ESD on LVD

丝印代码：2R110；DS25BR110 3.125 Gbps LVDS Buffer with Receive Equalization

1FEATURES 2• DC - 3.125 Gbps Low Jitter, High Noise Immunity, Low Power Operation • Four Levels of Receive Equalization Reduce ISI Jitter • On-Chip 100Ω Input and Output Termination Minimizes Insertion and Return Losses, Reduces Component Count, and Minimizes Board Space • 7 kV ESD on LVD

丝印代码：2R110；DS25BR110 3.125 Gbps LVDS Buffer with Receive Equalization

1FEATURES 2• DC - 3.125 Gbps Low Jitter, High Noise Immunity, Low Power Operation • Four Levels of Receive Equalization Reduce ISI Jitter • On-Chip 100Ω Input and Output Termination Minimizes Insertion and Return Losses, Reduces Component Count, and Minimizes Board Space • 7 kV ESD on LVD

丝印代码：2R110；DS25BR110 3.125 Gbps LVDS Buffer with Receive Equalization

1FEATURES 2• DC - 3.125 Gbps Low Jitter, High Noise Immunity, Low Power Operation • Four Levels of Receive Equalization Reduce ISI Jitter • On-Chip 100Ω Input and Output Termination Minimizes Insertion and Return Losses, Reduces Component Count, and Minimizes Board Space • 7 kV ESD on LVD

丝印代码：2R110；DS25BR110 3.125 Gbps LVDS Buffer with Receive Equalization

1FEATURES 2• DC - 3.125 Gbps Low Jitter, High Noise Immunity, Low Power Operation • Four Levels of Receive Equalization Reduce ISI Jitter • On-Chip 100Ω Input and Output Termination Minimizes Insertion and Return Losses, Reduces Component Count, and Minimizes Board Space • 7 kV ESD on LVD

丝印代码：2R110；DS25BR110 3.125 Gbps LVDS Buffer with Receive Equalization

1FEATURES 2• DC - 3.125 Gbps Low Jitter, High Noise Immunity, Low Power Operation • Four Levels of Receive Equalization Reduce ISI Jitter • On-Chip 100Ω Input and Output Termination Minimizes Insertion and Return Losses, Reduces Component Count, and Minimizes Board Space • 7 kV ESD on LVD

DS25BR120 3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis

1FEATURES 2• DC - 3.125 Gbps Low Jitter, High Noise Immunity, Low Power Operation • Four Levels of Transmit Pre-Emphasis Drive Lossy Backplanes and Cables • On-Chip 100Ω Input and Output Termination Minimizes Insertion and Return Losses, Reduces Component Count, and Minimizes Board Space

DS25BR100 / DS25BR101 3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization

1FEATURES 2• DC - 3.125 Gbps Low Jitter, High Noise Immunity, Low Power Operation • Receive Equalization Reduces ISI Jitter Due to Media Loss • Transmit Pre-Emphasis Drives Lossy Backplanes and Cables • On-Chip 100Ω Input and Output Termination: – Minimizes Insertion and Return Losses – R

具有发送预加重功能的 3.125Gbps LVDS 缓冲器

The DS25BR120 is a single channel 3.125 Gbps LVDS buffer optimized for high-speed signal transmission over lossy FR-4 printed circuit board backplanes and balanced metallic cables. Fully differential signal paths ensure exceptional signal integrity and noise immunity.The DS25BR120 features four leve • DC - 3.125 Gbps Low Jitter, High Noise Immunity, Low Power Operation\n• Four Levels of Transmit Pre-Emphasis Drive Lossy Backplanes and Cables\n• On-Chip 100Ω Input and Output Termination Minimizes Insertion and Return Losses, Reduces Component Count, and Minimizes Board Space \n• 7 kV ESD on LVDS;

丝印代码：2R120；DS25BR120 3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis

1FEATURES 2• DC - 3.125 Gbps Low Jitter, High Noise Immunity, Low Power Operation • Four Levels of Transmit Pre-Emphasis Drive Lossy Backplanes and Cables • On-Chip 100Ω Input and Output Termination Minimizes Insertion and Return Losses, Reduces Component Count, and Minimizes Board Space

丝印代码：2R120；DS25BR120 3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis

1FEATURES 2• DC - 3.125 Gbps Low Jitter, High Noise Immunity, Low Power Operation • Four Levels of Transmit Pre-Emphasis Drive Lossy Backplanes and Cables • On-Chip 100Ω Input and Output Termination Minimizes Insertion and Return Losses, Reduces Component Count, and Minimizes Board Space

丝印代码：2R120；DS25BR120 3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis

1FEATURES 2• DC - 3.125 Gbps Low Jitter, High Noise Immunity, Low Power Operation • Four Levels of Transmit Pre-Emphasis Drive Lossy Backplanes and Cables • On-Chip 100Ω Input and Output Termination Minimizes Insertion and Return Losses, Reduces Component Count, and Minimizes Board Space

丝印代码：2R120；DS25BR120 3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis

1FEATURES 2• DC - 3.125 Gbps Low Jitter, High Noise Immunity, Low Power Operation • Four Levels of Transmit Pre-Emphasis Drive Lossy Backplanes and Cables • On-Chip 100Ω Input and Output Termination Minimizes Insertion and Return Losses, Reduces Component Count, and Minimizes Board Space

DS25BR150 3.125 Gbps LVDS Buffer

1FEATURES 2• DC - 3.125 Gbps Low Jitter, High Noise Immunity, Low Power Operation • On-Chip 100 Ω Input and Output Termination Minimizes Insertion and Return Losses, Reduces Component Count and Minimizes Board Space • 7 kV ESD on LVDS I/O Pins Protects Adjoining Components • Small 3 mm x

DS25BR100 / DS25BR101 3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization

1FEATURES 2• DC - 3.125 Gbps Low Jitter, High Noise Immunity, Low Power Operation • Receive Equalization Reduces ISI Jitter Due to Media Loss • Transmit Pre-Emphasis Drives Lossy Backplanes and Cables • On-Chip 100Ω Input and Output Termination: – Minimizes Insertion and Return Losses – R

3.125Gbps LVDS 缓冲器

The DS25BR150 is a single channel 3.125 Gbps LVDS buffer optimized for high-speed signal transmission over printed circuit boards and balanced cables. Fully differential signal paths ensure exceptional signal integrity and noise immunity.The DS25BR150 is a buffer/repeater with very low power consump • DC - 3.125 Gbps Low Jitter, High Noise Immunity, Low Power Operation\n• On-Chip 100 Ω Input and Output Termination Minimizes Insertion and Return Losses, Reduces Component Count and Minimizes Board Space\n• 7 kV ESD on LVDS I/O Pins Protects Adjoining Components\n• Small 3 mm x 3 mm WSON-8 Space S;

丝印代码：2R150；DS25BR150 3.125 Gbps LVDS Buffer

1FEATURES 2• DC - 3.125 Gbps Low Jitter, High Noise Immunity, Low Power Operation • On-Chip 100 Ω Input and Output Termination Minimizes Insertion and Return Losses, Reduces Component Count and Minimizes Board Space • 7 kV ESD on LVDS I/O Pins Protects Adjoining Components • Small 3 mm x

丝印代码：2R150；DS25BR150 3.125 Gbps LVDS Buffer

1FEATURES 2• DC - 3.125 Gbps Low Jitter, High Noise Immunity, Low Power Operation • On-Chip 100 Ω Input and Output Termination Minimizes Insertion and Return Losses, Reduces Component Count and Minimizes Board Space • 7 kV ESD on LVDS I/O Pins Protects Adjoining Components • Small 3 mm x

丝印代码：2R150；DS25BR150 3.125 Gbps LVDS Buffer

1FEATURES 2• DC - 3.125 Gbps Low Jitter, High Noise Immunity, Low Power Operation • On-Chip 100 Ω Input and Output Termination Minimizes Insertion and Return Losses, Reduces Component Count and Minimizes Board Space • 7 kV ESD on LVDS I/O Pins Protects Adjoining Components • Small 3 mm x

丝印代码：2R150；DS25BR150 3.125 Gbps LVDS Buffer

1FEATURES 2• DC - 3.125 Gbps Low Jitter, High Noise Immunity, Low Power Operation • On-Chip 100 Ω Input and Output Termination Minimizes Insertion and Return Losses, Reduces Component Count and Minimizes Board Space • 7 kV ESD on LVDS I/O Pins Protects Adjoining Components • Small 3 mm x

DS25BR204 3.125 Gbps 1:4 LVDS Repeater with Transmit Pre-Emphasis and Receive Equalization

1FEATURES 2• DC - 3.125 Gbps Low Jitter, Low Skew, Low Power Operation • Pin Selectable Transmit Pre-Emphasis and Receive Equalization Eliminate Data Dependant Jitter • Wide Input Common Mode Range Allows DC- coupled Interface to LVDS, CML and LVPECL Drivers • Redundant Inputs • Integrat

具有发送预加重和接收均衡功能的 3.125Gbps 1:4 LVDS 中继器

• DC - 3.125 Gbps Low Jitter, Low Skew, Low Power Operation\n• Pin Selectable Transmit Pre-Emphasis and Receive Equalization Eliminate Data Dependant Jitter\n• Wide Input Common Mode Range Allows DC-coupled Interface to LVDS, CML and LVPECL Drivers\n• Redundant Inputs\n• Integrated 100Ω Input and Ou;

DS25BR204 3.125 Gbps 1:4 LVDS Repeater with Transmit Pre-Emphasis and Receive Equalization

1FEATURES 2• DC - 3.125 Gbps Low Jitter, Low Skew, Low Power Operation • Pin Selectable Transmit Pre-Emphasis and Receive Equalization Eliminate Data Dependant Jitter • Wide Input Common Mode Range Allows DC- coupled Interface to LVDS, CML and LVPECL Drivers • Redundant Inputs • Integrat

DS25BR204 3.125 Gbps 1:4 LVDS Repeater with Transmit Pre-Emphasis and Receive Equalization

1FEATURES 2• DC - 3.125 Gbps Low Jitter, Low Skew, Low Power Operation • Pin Selectable Transmit Pre-Emphasis and Receive Equalization Eliminate Data Dependant Jitter • Wide Input Common Mode Range Allows DC- coupled Interface to LVDS, CML and LVPECL Drivers • Redundant Inputs • Integrat

DS25BR400 Quad 2.5 Gbps CML Transceiver with Transmit De-Emphasis and Receive Equalization

1FEATURES 2• 250 Mbps – 2.5 Gbps Low Jitter Operation • Optional Fixed Input Equalization • Selectable Output De-Emphasis • Individual Loopback Controls • On-Chip Termination • +3.3V Supply • Lead-Less WQFN-60 Pin Package – (9 mm x9 mm x0.8 mm, 0.5 mm Pitch) • −40°C to +85°C Industrial Te

DS25BR440 3.125 Gbps Quad LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization

1FEATURES 2• DC - 3.125 Gbps Low Jitter, Low Skew, Low Power Operation • Pin Selectable Transmit Pre-Emphasis and Receive Equalization Eliminate Data Dependant Jitter • Wide Input Common Mode Voltage Range Allows DC-Coupled Interface to LVDS, CML and LVPECL Drivers • LOS Circuitry Detects

DS25BR440 3.125 Gbps Quad LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization

1FEATURES 2• DC - 3.125 Gbps Low Jitter, Low Skew, Low Power Operation • Pin Selectable Transmit Pre-Emphasis and Receive Equalization Eliminate Data Dependant Jitter • Wide Input Common Mode Voltage Range Allows DC-Coupled Interface to LVDS, CML and LVPECL Drivers • LOS Circuitry Detects

DS25BR440 3.125 Gbps Quad LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization

1FEATURES 2• DC - 3.125 Gbps Low Jitter, Low Skew, Low Power Operation • Pin Selectable Transmit Pre-Emphasis and Receive Equalization Eliminate Data Dependant Jitter • Wide Input Common Mode Voltage Range Allows DC-Coupled Interface to LVDS, CML and LVPECL Drivers • LOS Circuitry Detects

DS25BR440 3.125 Gbps Quad LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization

1FEATURES 2• DC - 3.125 Gbps Low Jitter, Low Skew, Low Power Operation • Pin Selectable Transmit Pre-Emphasis and Receive Equalization Eliminate Data Dependant Jitter • Wide Input Common Mode Voltage Range Allows DC-Coupled Interface to LVDS, CML and LVPECL Drivers • LOS Circuitry Detects

DS25BR440 3.125 Gbps Quad LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization

1FEATURES 2• DC - 3.125 Gbps Low Jitter, Low Skew, Low Power Operation • Pin Selectable Transmit Pre-Emphasis and Receive Equalization Eliminate Data Dependant Jitter • Wide Input Common Mode Voltage Range Allows DC-Coupled Interface to LVDS, CML and LVPECL Drivers • LOS Circuitry Detects

3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization

文件：871.93 Kbytes Page：19 Pages

3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization

文件：865.43 Kbytes Page：19 Pages

3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization

文件：490.88 Kbytes Page：16 Pages

3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization

文件：449.03 Kbytes Page：14 Pages