| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
DRA821U | DRA821 Jacinto™ Processors 1 Features Processor cores: • Dual 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2.0 GHz, 24K DMIPS – 1MB L2 shared cache per dual-core Cortex®- A72 cluster – 32KB L1 DCache and 48KB L1 ICache per A72 core • 4× Arm® Cortex®-R5F MCUs at up to 1.0 GHz with optional lockstep oper | TI 德州仪器 |   | |
DRA821U | DRA821 Jacinto™ Processors 1 Features Processor cores: • Dual 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2.0 GHz, 24K DMIPS – 1MB L2 shared cache per dual-core Cortex®- A72 cluster – 32KB L1 DCache and 48KB L1 ICache per A72 core • 4× Arm® Cortex®-R5F MCUs at up to 1.0 GHz with optional lockstep oper | TI 德州仪器 | | |
DRA821U | DRA821 Jacinto™ Processors 1 Features Processor cores: • Dual 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2.0 GHz, 24K DMIPS – 1MB L2 shared cache per dual-core Cortex®- A72 cluster – 32KB L1 DCache and 48KB L1 ICache per A72 core • 4× Arm® Cortex®-R5F MCUs at up to 1.0 GHz with optional lockstep oper | TI 德州仪器 | | |
DRA821U | DRA821 Jacinto??Processors 文件：5.01733 Mbytes Page：228 Pages | TI 德州仪器 | | |
丝印代码：DRA821U2CGBALM；DRA821 Jacinto™ Processors 1 Features Processor cores: • Dual 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2.0 GHz, 24K DMIPS – 1MB L2 shared cache per dual-core Cortex®- A72 cluster – 32KB L1 DCache and 48KB L1 ICache per A72 core • 4× Arm® Cortex®-R5F MCUs at up to 1.0 GHz with optional lockstep oper | TI 德州仪器 | | ||
丝印代码：DRA821U2CGBALM；DRA821 Jacinto™ Processors 1 Features Processor cores: • Dual 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2.0 GHz, 24K DMIPS – 1MB L2 shared cache per dual-core Cortex®- A72 cluster – 32KB L1 DCache and 48KB L1 ICache per A72 core • 4× Arm® Cortex®-R5F MCUs at up to 1.0 GHz with optional lockstep oper | TI 德州仪器 | | ||
丝印代码：DRA821U4TCBALMQ1；DRA821 Jacinto™ Processors 1 Features Processor cores: • Dual 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2.0 GHz, 24K DMIPS – 1MB L2 shared cache per dual-core Cortex®- A72 cluster – 32KB L1 DCache and 48KB L1 ICache per A72 core • 4× Arm® Cortex®-R5F MCUs at up to 1.0 GHz with optional lockstep oper | TI 德州仪器 | | ||
丝印代码：DRA821U4TCBALMQ1；DRA821 Jacinto™ Processors 1 Features Processor cores: • Dual 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2.0 GHz, 24K DMIPS – 1MB L2 shared cache per dual-core Cortex®- A72 cluster – 32KB L1 DCache and 48KB L1 ICache per A72 core • 4× Arm® Cortex®-R5F MCUs at up to 1.0 GHz with optional lockstep oper | TI 德州仪器 | | ||
丝印代码：DRA821U4TCBALMQ1；DRA821 Jacinto™ Processors 1 Features Processor cores: • Dual 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2.0 GHz, 24K DMIPS – 1MB L2 shared cache per dual-core Cortex®- A72 cluster – 32KB L1 DCache and 48KB L1 ICache per A72 core • 4× Arm® Cortex®-R5F MCUs at up to 1.0 GHz with optional lockstep oper | TI 德州仪器 | | ||
丝印代码：DRA821U4TCBALMQ1；DRA821 Jacinto™ Processors 1 Features Processor cores: • Dual 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2.0 GHz, 24K DMIPS – 1MB L2 shared cache per dual-core Cortex®- A72 cluster – 32KB L1 DCache and 48KB L1 ICache per A72 core • 4× Arm® Cortex®-R5F MCUs at up to 1.0 GHz with optional lockstep oper | TI 德州仪器 | | ||
丝印代码：DRA821U4TCBALMQ1；DRA821 Jacinto™ Processors 1 Features Processor cores: • Dual 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2.0 GHz, 24K DMIPS – 1MB L2 shared cache per dual-core Cortex®- A72 cluster – 32KB L1 DCache and 48KB L1 ICache per A72 core • 4× Arm® Cortex®-R5F MCUs at up to 1.0 GHz with optional lockstep oper | TI 德州仪器 | | ||
丝印代码：DRA821U4TCBALMQ1；DRA821 Jacinto™ Processors 1 Features Processor cores: • Dual 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2.0 GHz, 24K DMIPS – 1MB L2 shared cache per dual-core Cortex®- A72 cluster – 32KB L1 DCache and 48KB L1 ICache per A72 core • 4× Arm® Cortex®-R5F MCUs at up to 1.0 GHz with optional lockstep oper | TI 德州仪器 | | ||
丝印代码：DRA821U4TGBALM；DRA821 Jacinto™ Processors 1 Features Processor cores: • Dual 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2.0 GHz, 24K DMIPS – 1MB L2 shared cache per dual-core Cortex®- A72 cluster – 32KB L1 DCache and 48KB L1 ICache per A72 core • 4× Arm® Cortex®-R5F MCUs at up to 1.0 GHz with optional lockstep oper | TI 德州仪器 | | ||
丝印代码：DRA821U4TGBALM；DRA821 Jacinto™ Processors 1 Features Processor cores: • Dual 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2.0 GHz, 24K DMIPS – 1MB L2 shared cache per dual-core Cortex®- A72 cluster – 32KB L1 DCache and 48KB L1 ICache per A72 core • 4× Arm® Cortex®-R5F MCUs at up to 1.0 GHz with optional lockstep oper | TI 德州仪器 | | ||
丝印代码：DRA821U4TGBALM；DRA821 Jacinto™ Processors 1 Features Processor cores: • Dual 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2.0 GHz, 24K DMIPS – 1MB L2 shared cache per dual-core Cortex®- A72 cluster – 32KB L1 DCache and 48KB L1 ICache per A72 core • 4× Arm® Cortex®-R5F MCUs at up to 1.0 GHz with optional lockstep oper | TI 德州仪器 | | ||
丝印代码：DRA821U4TGBALM；DRA821 Jacinto™ Processors 1 Features Processor cores: • Dual 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2.0 GHz, 24K DMIPS – 1MB L2 shared cache per dual-core Cortex®- A72 cluster – 32KB L1 DCache and 48KB L1 ICache per A72 core • 4× Arm® Cortex®-R5F MCUs at up to 1.0 GHz with optional lockstep oper | TI 德州仪器 | | ||
DRA821 Jacinto™ Processors 1 Features Processor cores: • Dual 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2.0 GHz, 24K DMIPS – 1MB L2 shared cache per dual-core Cortex®- A72 cluster – 32KB L1 DCache and 48KB L1 ICache per A72 core • 4× Arm® Cortex®-R5F MCUs at up to 1.0 GHz with optional lockstep oper | TI 德州仪器 | | ||
DRA821 Jacinto™ Processors 1 Features Processor cores: • Dual 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2.0 GHz, 24K DMIPS – 1MB L2 shared cache per dual-core Cortex®- A72 cluster – 32KB L1 DCache and 48KB L1 ICache per A72 core • 4× Arm® Cortex®-R5F MCUs at up to 1.0 GHz with optional lockstep oper | TI 德州仪器 | | ||
DRA821 Jacinto™ Processors 1 Features Processor cores: • Dual 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2.0 GHz, 24K DMIPS – 1MB L2 shared cache per dual-core Cortex®- A72 cluster – 32KB L1 DCache and 48KB L1 ICache per A72 core • 4× Arm® Cortex®-R5F MCUs at up to 1.0 GHz with optional lockstep oper | TI 德州仪器 | | ||
DRA821 Jacinto™ Processors 1 Features Processor cores: • Dual 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2.0 GHz, 24K DMIPS – 1MB L2 shared cache per dual-core Cortex®- A72 cluster – 32KB L1 DCache and 48KB L1 ICache per A72 core • 4× Arm® Cortex®-R5F MCUs at up to 1.0 GHz with optional lockstep oper | TI 德州仪器 | | ||
DRA821 Jacinto™ Processors 1 Features Processor cores: • Dual 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2.0 GHz, 24K DMIPS – 1MB L2 shared cache per dual-core Cortex®- A72 cluster – 32KB L1 DCache and 48KB L1 ICache per A72 core • 4× Arm® Cortex®-R5F MCUs at up to 1.0 GHz with optional lockstep oper | TI 德州仪器 | | ||
DRA821 Jacinto™ Processors 1 Features Processor cores: • Dual 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2.0 GHz, 24K DMIPS – 1MB L2 shared cache per dual-core Cortex®- A72 cluster – 32KB L1 DCache and 48KB L1 ICache per A72 core • 4× Arm® Cortex®-R5F MCUs at up to 1.0 GHz with optional lockstep oper | TI 德州仪器 | | ||
DRA821 Jacinto™ Processors 1 Features Processor cores: • Dual 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2.0 GHz, 24K DMIPS – 1MB L2 shared cache per dual-core Cortex®- A72 cluster – 32KB L1 DCache and 48KB L1 ICache per A72 core • 4× Arm® Cortex®-R5F MCUs at up to 1.0 GHz with optional lockstep oper | TI 德州仪器 | | ||
DRA821 Jacinto™ Processors 1 Features Processor cores: • Dual 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2.0 GHz, 24K DMIPS – 1MB L2 shared cache per dual-core Cortex®- A72 cluster – 32KB L1 DCache and 48KB L1 ICache per A72 core • 4× Arm® Cortex®-R5F MCUs at up to 1.0 GHz with optional lockstep oper | TI 德州仪器 | | ||
DRA821 Jacinto™ Processors 1 Features Processor cores: • Dual 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2.0 GHz, 24K DMIPS – 1MB L2 shared cache per dual-core Cortex®- A72 cluster – 32KB L1 DCache and 48KB L1 ICache per A72 core • 4× Arm® Cortex®-R5F MCUs at up to 1.0 GHz with optional lockstep oper | TI 德州仪器 | | ||
DRA821 Jacinto™ Processors 1 Features Processor cores: • Dual 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2.0 GHz, 24K DMIPS – 1MB L2 shared cache per dual-core Cortex®- A72 cluster – 32KB L1 DCache and 48KB L1 ICache per A72 core • 4× Arm® Cortex®-R5F MCUs at up to 1.0 GHz with optional lockstep oper | TI 德州仪器 | | ||
DRA821 Jacinto™ Processors 1 Features Processor cores: • Dual 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2.0 GHz, 24K DMIPS – 1MB L2 shared cache per dual-core Cortex®- A72 cluster – 32KB L1 DCache and 48KB L1 ICache per A72 core • 4× Arm® Cortex®-R5F MCUs at up to 1.0 GHz with optional lockstep oper | TI 德州仪器 | | ||
Automotive gateway SoC with dual Arm® Cortex®-A72, quad Cortex-R5F, four-port Ethernet switch, PCIe | TI 德州仪器 | | ||
POWER INDUCTOR ●FEATURE 1. Excellent solder heat resistance(add “C” is for high current type) 2. Low voltage drops and small variations inductance ●APPLICATION 1. DC power supply circuits 2. Power line choke coils…etc | AITSEMI 创瑞科技 | | ||
SHIELDED SMT POWER INDUCTORS ● FEATURE Various high power inductor are Superior to be high saturation for surface mounting ● APPLICATIONS 2 DC/DC converter power supply, Telecommunication equipment | PRODUCTWELL | | ||
Mill-Max Spring-loaded Connectors Minimize Noise 文件：2.45329 Mbytes Page：11 Pages | MILL-MAX | | ||
3M??Scotch짰 Label Protection Tape 821 文件：577.02 Kbytes Page：6 Pages | 3M | | ||
Panel Mount , for 5x20mm Fuses 文件：179.38 Kbytes Page：1 Pages | LITTELFUSE 力特 | |
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
TI |
25+ |
433-FCBGA(17.2x17.2) |
7786 |
正规渠道,免费送样。支持账期,BOM一站式配齐 |
|||
TI |
25+ |
433-FCBGA(17.2x17.2) |
7786 |
正规渠道,免费送样。支持账期,BOM一站式配齐 |
|||
TI/德州仪器 |
25+ |
原厂封装 |
10280 |
原厂授权代理,专注军工、汽车、医疗、工业、新能源！ |
|||
Texas Instruments |
24+25+ |
16500 |
全新原厂原装现货!受权代理!可送样可提供技术支持! |
||||
TI/德州仪器 |
25+ |
原厂封装 |
9999 |
||||
TI |
25+ |
FCBGA (ALF) |
6000 |
原厂原装,价格优势 |
|||
Texas Instruments |
25+ |
827-BFBGA FCBGA |
9350 |
独立分销商 公司只做原装 诚心经营 免费试样正品保证 |
|||
====无==== |
24+ |
NA |
10000 |
低于市场价,实单必成,QQ1562321770 |
|||
TI/德州仪器 |
25+ |
原厂封装 |
10280 |
||||
TI |
25+ |
30000 |
原装现货,支持实单 |
DRA821U芯片相关品牌
DRA821U规格书下载地址
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DRA821U数据表相关新闻
DRA624AIZKKQI
DRA624AIZKKQI
2023-7-6DRC23-64PAA-N010
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2013-3-24
DdatasheetPDF页码索引
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