8-Bit Parallel In/Serial Output Shift Registers

General Description This device is an 8-bit serial shift register which shifts data in the direction of QA toward QH when clocked. Parallel-in access is made available by eight individual direct data inputs, which are enabled by a low level at the shift/load input. These registers also feature

8-Bit Parallel In/Serial Output Shift Registers

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封装/外壳：16-DIP（0.300"，7.62mm） 功能：并行或串行至串行 包装：管件 描述：IC REGISTER PAR-IN/SER-OUT 16DIP 集成电路（IC） 移位寄存器

8-Bit Parallel In/Serial Output Shift Registers

8-Bit Parallel In/Serial Output Shift Registers

General Description This device is an 8-bit serial shift register which shifts data in the direction of QA toward QH when clocked. Parallel-in access is made available by eight individual direct data inputs, which are enabled by a low level at the shift/load input. These registers also feature

8-Bit Parallel In/Serial Output Shift Registers

General Description This device is an 8-bit serial shift register which shifts data in the direction of QA toward QH when clocked. Parallel-in access is made available by eight individual direct data inputs, which are enabled by a low level at the shift/load input. These registers also feature

8-Bit Parallel In/Serial Output Shift Registers

General Description This device is an 8-bit serial shift register which shifts data in the direction of QA toward QH when clocked. Parallel-in access is made available by eight individual direct data inputs, which are enabled by a low level at the shift/load input. These registers also feature

8-Bit Parallel In/Serial Output Shift Registers

General Description This device is an 8-bit serial shift register which shifts data in the direction of QA toward QH when clocked. Parallel-in access is made available by eight individual direct data inputs, which are enabled by a low level at the shift/load input. These registers also featur

8-Bit Parallel In/Serial Output Shift Registers

General Description This device is an 8-bit serial shift register which shifts data in the direction of QA toward QH when clocked. Parallel-in access is made available by eight individual direct data inputs, which are enabled by a low level at the shift/load input. These registers also featur

8-BIT PARALLEL-TO-SERIAL SHIFT REGISTER

BCD DECADE COUNTERS/ 4-BIT BINARY COUNTERS

LOW POWER SCHOTTKY