Inverting Octal Bus Transceiver

General Description This inverting octal bus transceiver is designed for asynchronous two-way communication between data busses. This device transmits data from the A bus to the B bus or from the B bus to the A bus depending upon the level at the direction control (DIR) input. The enable input (G

Inverting Octal Bus Transceiver

General Description This inverting octal bus transceiver is designed for asynchronous two-way communication between data busses. This device transmits data from the A bus to the B bus or from the B bus to the A bus depending upon the level at the direction control (DIR) input. The enable input (G

Inverting Octal Bus Transceiver

General Description This inverting octal bus transceiver is designed for asynchronous two-way communication between data busses. This device transmits data from the A bus to the B bus or from the B bus to the A bus depending upon the level at the direction control (DIR) input. The enable input (G

Inverting Octal Bus Transceiver

General Description\nThis inverting octal bus transceiver is designed for asynchronous two-way communication between data busses. This device transmits data from the A bus to the B bus or from the B bus to the A bus depending upon the level at the direction control (DIR) input. The enable input (G) ■ Advanced Oxide-isolated Ion-implanted Schottky TTL process\n■ Switching performance is guaranteed over full temperature and VCC supply range\n■ Switching performance specified at 50 pF\n■ PNP input design reduces input loading;

IC TRANSCVR INVERT 5.5V 20DIP

封装/外壳：20-SOIC（0.295"，7.50mm 宽） 包装：管件 描述：IC TXRX INVERT 5.5V 20SOIC 集成电路（IC） 缓冲器，驱动器，接收器，收发器

IC TRANSCVR INVERT 5.5V 20SOIC

封装/外壳：20-SOIC（0.295"，7.50mm 宽） 包装：管件 描述：IC TXRX INVERT 5.5V 20SOIC 集成电路（IC） 缓冲器，驱动器，接收器，收发器

Inverting Octal Bus Transceiver

General Description This inverting octal bus transceiver is designed for asynchronous two-way communication between data busses. This device transmits data from the A bus to the B bus or from the B bus to the A bus depending upon the level at the direction control (DIR) input. The enable input (G

Octal Bus Transceiver (3-State)

文件：396.42 Kbytes Page：2 Pages

OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

文件：112.77 Kbytes Page：7 Pages

OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

文件：112.77 Kbytes Page：7 Pages