5-TAP, 3.3V CMOS-INTERFACED FIXED DELAY LINE

FUNCTIONAL DESCRIPTION The DDU8C3-series device is a 5-tap digitally buffered delay line. The signal input (IN) is reproduced at the outputs (T1-T5), shifted in time by an amount determined by the device dash number (See Table). For dash numbers 5020 and above, the total delay of the line is meas