丝印代码：8162；DACxx6x Dual 16-, 14-, 12-Bit, Low-Power, Buffered, Voltage-Output DACs With 2.5-V, 4-PPM/°C Internal Reference

1 Features 1• Relative Accuracy: – DAC756x (12-Bit): 0.3 LSB INL – DAC816x (14-Bit): 1 LSB INL – DAC856x (16-Bit): 4 LSB INL • Glitch Impulse: 0.1 nV-s • Bidirectional Reference: Input or 2.5-V Output – Output Disabled by Default – ±5-mV Initial Accuracy (Max) – 4-ppm°C Temperature Drift

DUAL 16-/14-/12-BIT, ULTRALOW-GLITCH, LOW-POWER, BUFFERED, VOLTAGE-OUTPUT

文件：1.31609 Mbytes Page：56 Pages

DUAL 16-/14-/12-BIT, ULTRALOW-GLITCH, LOW-POWER, BUFFERED, VOLTAGE-OUTPUT DAC WITH 2.5-V, 4-PPM/째C INTERNAL REFERENCE IN SMALL 3-MM 횞 3-MM SON

文件：1.88265 Mbytes Page：58 Pages

Internal Reference

文件：1.9843 Mbytes Page：60 Pages

封装/外壳：10-TFSOP，10-MSOP（0.118"，3.00mm 宽） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC DAC 14BIT V-OUT 10VSSOP 集成电路（IC） 数模转换器（DAC）

丝印代码：8162；DACxx6x Dual 16-, 14-, 12-Bit, Low-Power, Buffered, Voltage-Output DACs With 2.5-V, 4-PPM/°C Internal Reference

1 Features 1• Relative Accuracy: – DAC756x (12-Bit): 0.3 LSB INL – DAC816x (14-Bit): 1 LSB INL – DAC856x (16-Bit): 4 LSB INL • Glitch Impulse: 0.1 nV-s • Bidirectional Reference: Input or 2.5-V Output – Output Disabled by Default – ±5-mV Initial Accuracy (Max) – 4-ppm°C Temperature Drift

5 V, 5 V and 8 V Triple-Voltage Regulator with Disable and Reset Functions

DESCRIPTION The STV8162 and STV8162D are monolithic triple positive voltage regulators designed to provide three fixed precision output voltages of 5 V, 5 V and 8 V for currents up to 0.6 A. An internal reset circuit generates a reset pulse when the voltage of Output 1 drops below the regulated

5 V, 5 V and 8 V Triple-Voltage Regulator with Disable and Reset Functions

DESCRIPTION The STV8162 and STV8162D are monolithic triple positive voltage regulators designed to provide three fixed precision output voltages of 5 V, 5 V and 8 V for currents up to 0.6 A. An internal reset circuit generates a reset pulse when the voltage of Output 1 drops below the regulated

2.488 Gbit/sec SONET/SDH 1:16 Demux with Clock Recovery

General Description The VSC8162 combines a clock recovery unit (CRU) with a 1:16 demultiplexer on a single chip to directly generate 16-bit wide data from an incoming 2.488Gb/s NRZ data stream. An on-chip Phase Locked Loop (PLL) generates a 2.488GHz clock which remains phase locked to the incomin

T1/CEPT Quad Port T1/E1

文件：268.05 Kbytes Page：2 Pages

LED Displays Numeric 7-segment

文件：295.65 Kbytes Page：7 Pages