General Description

The VSC8162 combines a clock recovery unit (CRU) with a 1:16 demultiplexer on a single chip to directly generate 16-bit wide data from an incoming 2.488Gb/s NRZ data stream. An on-chip Phase Locked Loop (PLL) generates a 2.488GHz clock which remains phase locked to the incoming data. The incoming data is retimed and demultiplexed to a 16-bit word. A Loss of Lock (LOL) signal indicates gross conditions where incoming data no longer has sufficient transitions to keep the CRU in lock.

Features

• 2.488Gb/s 1:16 Demux with Integrated Clock and Data Recovery

• Recovered Clock and Data Available

• Monolithic Phase Locked Loop

• Digitally Adjustable Serial Data Sampling Point

• Differential Low Speed Outputs

• Differential/Single-ended Reference Clock

• Loss of Lock Detection

• Meets SONET OC-48 and SDH STM-16 Jitter Tolerance Requirements