丝印代码：8162；DACxx6x Dual 16-, 14-, 12-Bit, Low-Power, Buffered, Voltage-Output DACs With 2.5-V, 4-PPM/°C Internal Reference

1 Features 1• Relative Accuracy: – DAC756x (12-Bit): 0.3 LSB INL – DAC816x (14-Bit): 1 LSB INL – DAC856x (16-Bit): 4 LSB INL • Glitch Impulse: 0.1 nV-s • Bidirectional Reference: Input or 2.5-V Output – Output Disabled by Default – ±5-mV Initial Accuracy (Max) – 4-ppm°C Temperature Drift

5 V, 5 V and 8 V Triple-Voltage Regulator with Disable and Reset Functions

DESCRIPTION The STV8162 and STV8162D are monolithic triple positive voltage regulators designed to provide three fixed precision output voltages of 5 V, 5 V and 8 V for currents up to 0.6 A. An internal reset circuit generates a reset pulse when the voltage of Output 1 drops below the regulated

5 V, 5 V and 8 V Triple-Voltage Regulator with Disable and Reset Functions

DESCRIPTION The STV8162 and STV8162D are monolithic triple positive voltage regulators designed to provide three fixed precision output voltages of 5 V, 5 V and 8 V for currents up to 0.6 A. An internal reset circuit generates a reset pulse when the voltage of Output 1 drops below the regulated

2.488 Gbit/sec SONET/SDH 1:16 Demux with Clock Recovery

General Description The VSC8162 combines a clock recovery unit (CRU) with a 1:16 demultiplexer on a single chip to directly generate 16-bit wide data from an incoming 2.488Gb/s NRZ data stream. An on-chip Phase Locked Loop (PLL) generates a 2.488GHz clock which remains phase locked to the incomin

T1/CEPT Quad Port T1/E1

文件：268.05 Kbytes Page：2 Pages

LED Displays Numeric 7-segment

文件：295.65 Kbytes Page：7 Pages