10-Bit Current output D to A Converter

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10-Bit Current output D to A Converter

Dual 10-bit DAC, up to 125 Msps

Features and benefits  Dual 10-bit resolution  125 Msps update rate  Single 3.3 V supply  Dual-port or Interleaved data modes  1.8 V, 3.3 V and 5 V compatible digital inputs  Internal and external reference  2 mA to 20 mA full-scale output current  Typical 185 mW power dissipation

Dual 10 bits DAC, up to 160 MHz, 2 x interpolation

Features Dual 10-bit resolution Spurious Free Dynamic Range (SFDR) = 80 dBc at 2.5 MHz Input data rate up to 80 MHz 2  interpolation filter Output data rate up to 160 Mhz Single 3.3 V power supply Low noise capacitor free integrated Phase-Locked Loop (PLL) Low power dissipation 

Dual 10 bits DAC, up to 160 MHz, 2 x interpolation

General description The DAC1003D160 is optimized to reduce architecture complexity and overall system cost. The Digital-to-Analog Converter (DAC) leads dynamic performance in multi-carrier support because of its direct IF conversion capabilities. With an internal sampling rate up to 160 MHz, th

Dual 10 bits DAC, up to 160 MHz, 2 x interpolation

Dual 10 bits DAC, up to 160 MHz, 2 x interpolation

Dual 10 bits DAC, up to 160 MHz, 2 x interpolation

General description The DAC1003D160 is optimized to reduce architecture complexity and overall system cost. The Digital-to-Analog Converter (DAC) leads dynamic performance in multi-carrier support because of its direct IF conversion capabilities. With an internal sampling rate up to 160 MHz, th

Dual 10 bits DAC, up to 160 MHz, 2 x interpolation

Features Dual 10-bit resolution Spurious Free Dynamic Range (SFDR) = 80 dBc at 2.5 MHz Input data rate up to 80 MHz 2  interpolation filter Output data rate up to 160 Mhz Single 3.3 V power supply Low noise capacitor free integrated Phase-Locked Loop (PLL) Low power dissipation 

Dual 10-bit DAC, up to 650 Msps; 2 4 and 8 interpolating

Features and benefits  Dual 10-bit resolution  650 Msps maximum update rate  Selectable 2, 4 or 8 interpolation filters  Input data rate up to 160 Msps  Very low noise cap-free integrated PLL  32-bit programmable NCO frequency  Dual-port or Interleaved data modes  1.8 V and 3.3

Dual 10-bit DAC, up to 650 Msps; 2쨈 4쨈 and 8쨈 interpolating

Dual 10-bit DAC, up to 650 Msps; 2 4 and 8 interpolating

Features and benefits  Dual 10-bit resolution  650 Msps maximum update rate  Selectable 2, 4 or 8 interpolation filters  Input data rate up to 160 Msps  Very low noise cap-free integrated PLL  32-bit programmable NCO frequency  Dual-port or Interleaved data modes  1.8 V and 3.3

Dual 10-bit DAC, up to 650 Msps; 2쨈 4쨈 and 8쨈 interpolating

Dual 10-bit DAC, up to 650 Msps; 2쨈 4쨈 and 8쨈 interpolating

Dual 10-bit DAC, up to 750 Msps; 4x and 8x interpolating

Features and benefits  Dual 10-bit resolution  750 Msps maximum update rate  Selectable 4 or 8 interpolation filters  Input data rate up to 185 Msps  Very low noise cap-free integrated PLL  32-bit programmable NCO frequency  Dual port or Interleaved data modes  1.8 V and 3.3 V po

Dual 10-bit DAC, up to 750 Msps; 4x and 8x interpolating

Features and benefits  Dual 10-bit resolution  750 Msps maximum update rate  Selectable 4 or 8 interpolation filters  Input data rate up to 185 Msps  Very low noise cap-free integrated PLL  32-bit programmable NCO frequency  Dual port or Interleaved data modes  1.8 V and 3.3 V po

Dual 10-bit DAC; up to 650 Msps; 2, 4 or 8 interpolating with JESD204A interface

 Dual 10-bit resolution  650 Msps maximum update rate  Selectable 2, 4 or 8 interpolation filters  Input data rate up to 312.5 Msps  Very low noise cap free integrated PLL  32-bit programmable NCO frequency  Four JESD204A serial input lanes  1.8 V and 3.3 V power supplies  LVD

Dual 10-bit DAC; up to 650 Msps; 2, 4 or 8 interpolating with JESD204A interface

 Dual 10-bit resolution  650 Msps maximum update rate  Selectable 2, 4 or 8 interpolation filters  Input data rate up to 312.5 Msps  Very low noise cap free integrated PLL  32-bit programmable NCO frequency  Four JESD204A serial input lanes  1.8 V and 3.3 V power supplies  LVD

Dual 10-bit DAC; up to 750 Msps; 2, 4 or 8 interpolating with JESD204A interface

 Dual 10-bit resolution  750 Msps maximum update rate  Selectable 2, 4 or 8 interpolation filters  Input data rate up to 312.5 Msps  Very low-noise cap-free integrated PLL  32-bit programmable NCO frequency  Four JESD204A serial input lanes  1.8 V and 3.3 V power supplies  LVD

Dual 10-bit DAC; up to 750 Msps; 2, 4 or 8 interpolating with JESD204A interface

 Dual 10-bit resolution  750 Msps maximum update rate  Selectable 2, 4 or 8 interpolation filters  Input data rate up to 312.5 Msps  Very low-noise cap-free integrated PLL  32-bit programmable NCO frequency  Four JESD204A serial input lanes  1.8 V and 3.3 V power supplies  LVD

DOUBLE-BUFFERED D TO A CONVERTERS

文件：854.89 Kbytes Page：23 Pages

DOUBLE-BUFFERED D TO A CONVERTERS

文件：854.89 Kbytes Page：23 Pages

DOUBLE-BUFFERED D TO A CONVERTERS

文件：854.89 Kbytes Page：23 Pages

DOUBLE-BUFFERED D TO A CONVERTERS

文件：854.89 Kbytes Page：23 Pages

DOUBLE-BUFFERED D TO A CONVERTERS

文件：854.89 Kbytes Page：23 Pages

Dual 10-bit DAC, up to 125 Msps

Dual 10-bit DAC, up to 125 Msps

Dual 10-bit DAC, up to 125 Msps

文件：382.1 Kbytes Page：25 Pages

Dual 10-bit DAC, up to 125 Msps

Dual 10-bit DAC, up to 125 Msps

Dual 10-bit DAC, up to 125 Msps

文件：382.1 Kbytes Page：25 Pages

封装/外壳：48-LQFP 包装：卷带（TR） 描述：IC DAC 10BIT A-OUT 48LQFP 集成电路（IC） 数模转换器（DAC）

封装/外壳：48-LQFP 包装：卷带（TR） 描述：IC DAC 10BIT A-OUT 48LQFP 集成电路（IC） 数模转换器（DAC）

DOUBLE-BUFFERED D TO A CONVERTERS

文件：854.89 Kbytes Page：23 Pages

DOUBLE-BUFFERED D TO A CONVERTERS

文件：854.89 Kbytes Page：23 Pages

DOUBLE-BUFFERED D TO A CONVERTERS

文件：854.89 Kbytes Page：23 Pages

DOUBLE-BUFFERED D TO A CONVERTERS

文件：854.89 Kbytes Page：23 Pages

DOUBLE-BUFFERED D TO A CONVERTERS

文件：854.89 Kbytes Page：23 Pages

DOUBLE-BUFFERED D TO A CONVERTERS

文件：854.89 Kbytes Page：23 Pages

uP Compatible, Double-Buffered D to A Converters

文件：369.16 Kbytes Page：22 Pages

DOUBLE-BUFFERED D TO A CONVERTERS

文件：854.89 Kbytes Page：23 Pages

uP Compatible, Double-Buffered D to A Converters

文件：369.16 Kbytes Page：22 Pages

DOUBLE-BUFFERED D TO A CONVERTERS

文件：854.89 Kbytes Page：23 Pages

uP Compatible, Double-Buffered D to A Converters

文件：369.16 Kbytes Page：22 Pages

DOUBLE-BUFFERED D TO A CONVERTERS

文件：854.89 Kbytes Page：23 Pages

uP Compatible, Double-Buffered D to A Converters

文件：369.16 Kbytes Page：22 Pages

DOUBLE-BUFFERED D TO A CONVERTERS

文件：854.89 Kbytes Page：23 Pages

DOUBLE-BUFFERED D TO A CONVERTERS

文件：854.89 Kbytes Page：23 Pages

uP Compatible, Double-Buffered D to A Converters

文件：369.16 Kbytes Page：22 Pages

uP Compatible, Double-Buffered D to A Converters

文件：369.16 Kbytes Page：22 Pages

DOUBLE-BUFFERED D TO A CONVERTERS

文件：854.89 Kbytes Page：23 Pages

Dual 10-bit DAC; up to 650 Msps; 2횞, 4횞 or 8횞 interpolating with JESD204A interface

Dual 10-bit DAC up to 650 Msps; 2횞, 4횞 or 8횞 interpolating with JESD204A interface

Dual 10-bit DAC; up to 650 Msps; 2횞, 4횞 or 8횞 interpolating with JESD204A interface

Dual 10-bit DAC; up to 650 Msps; 2횞, 4횞 or 8횞 interpolating with JESD204A interface

Dual 10-bit DAC up to 650 Msps; 2횞, 4횞 or 8횞 interpolating with JESD204A interface

Dual 10-bit DAC up to 750 Msps 2횞, 4횞 or 8횞 interpolating with JESD204A interface

Dual 10-bit DAC; up to 750 Msps; 2횞, 4횞 or 8횞 interpolating

Dual 10-bit DAC; up to 750 Msps; 2횞, 4횞 or 8횞 interpolating

Dual 10-bit DAC; up to 750 Msps; 2횞, 4횞 or 8횞 interpolating