64K x 8 Reprogrammable Registered PROM

Features • CMOS for optimum speed/power • Windowed for reprogrammability • High speed — tSA = 45 ns — tCO = 15 ns • Low power — 120 mA • On-chip, edge-triggered output registers • Programmable synchronous or asynchronous output enable • EPROM technology, 100 programma

64K x 8 Reprogrammable Registered PROM

Features • CMOS for optimum speed/power • Windowed for reprogrammability • High speed — tSA = 45 ns — tCO = 15 ns • Low power — 120 mA • On-chip, edge-triggered output registers • Programmable synchronous or asynchronous output enable • EPROM technology, 100 programma

64K x 8 Reprogrammable Registered PROM

Features • CMOS for optimum speed/power • Windowed for reprogrammability • High speed — tSA = 45 ns — tCO = 15 ns • Low power — 120 mA • On-chip, edge-triggered output registers • Programmable synchronous or asynchronous output enable • EPROM technology, 100 programma

64K x 8 Reprogrammable Registered PROM

Features • CMOS for optimum speed/power • Windowed for reprogrammability • High speed — tSA = 45 ns — tCO = 15 ns • Low power — 120 mA • On-chip, edge-triggered output registers • Programmable synchronous or asynchronous output enable • EPROM technology, 100 programma

64K x 8 Reprogrammable Registered PROM

Features • CMOS for optimum speed/power • Windowed for reprogrammability • High speed — tSA = 45 ns — tCO = 15 ns • Low power — 120 mA • On-chip, edge-triggered output registers • Programmable synchronous or asynchronous output enable • EPROM technology, 100 programma

64K x 8 Reprogrammable Registered PROM

Features • CMOS for optimum speed/power • Windowed for reprogrammability • High speed — tSA = 45 ns — tCO = 15 ns • Low power — 120 mA • On-chip, edge-triggered output registers • Programmable synchronous or asynchronous output enable • EPROM technology, 100 programma