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CY7C1371D价格
参考价格：￥115.2244
型号：CY7C1371D-100AXC 品牌：CYPRESS 备注：这里有CY7C1371D多少钱，2025年最近7天走势，今日出价，今日竞价，CY7C1371D批发/采购报价，CY7C1371D行情走势销售排行榜，CY7C1371D报价。| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
CY7C1371D | 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture Functional Description[1] The CY7C1371D/CY7C1373D is a 3.3V, 512K x 36/1 Mbit x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1371D/ CY7C1373D is equipped with the advanced No | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 |   | |
CY7C1371D | 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL??Architecture 文件：1.01162 Mbytes Page：29 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | |
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture Functional Description[1] The CY7C1371D/CY7C1373D is a 3.3V, 512K x 36/1 Mbit x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1371D/ CY7C1373D is equipped with the advanced No | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture Functional Description[1] The CY7C1371D/CY7C1373D is a 3.3V, 512K x 36/1 Mbit x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1371D/ CY7C1373D is equipped with the advanced No | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture Functional Description[1] The CY7C1371D/CY7C1373D is a 3.3V, 512K x 36/1 Mbit x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1371D/ CY7C1373D is equipped with the advanced No | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture Functional Description[1] The CY7C1371D/CY7C1373D is a 3.3V, 512K x 36/1 Mbit x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1371D/ CY7C1373D is equipped with the advanced No | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture Functional Description[1] The CY7C1371D/CY7C1373D is a 3.3V, 512K x 36/1 Mbit x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1371D/ CY7C1373D is equipped with the advanced No | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture Functional Description[1] The CY7C1371D/CY7C1373D is a 3.3V, 512K x 36/1 Mbit x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1371D/ CY7C1373D is equipped with the advanced No | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture Functional Description[1] The CY7C1371D/CY7C1373D is a 3.3V, 512K x 36/1 Mbit x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1371D/ CY7C1373D is equipped with the advanced No | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture Functional Description[1] The CY7C1371D/CY7C1373D is a 3.3V, 512K x 36/1 Mbit x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1371D/ CY7C1373D is equipped with the advanced No | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture Functional Description[1] The CY7C1371D/CY7C1373D is a 3.3V, 512K x 36/1 Mbit x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1371D/ CY7C1373D is equipped with the advanced No | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture Functional Description[1] The CY7C1371D/CY7C1373D is a 3.3V, 512K x 36/1 Mbit x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1371D/ CY7C1373D is equipped with the advanced No | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture Functional Description[1] The CY7C1371D/CY7C1373D is a 3.3V, 512K x 36/1 Mbit x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1371D/ CY7C1373D is equipped with the advanced No | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture Functional Description[1] The CY7C1371D/CY7C1373D is a 3.3V, 512K x 36/1 Mbit x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1371D/ CY7C1373D is equipped with the advanced No | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture Functional Description[1] The CY7C1371D/CY7C1373D is a 3.3V, 512K x 36/1 Mbit x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1371D/ CY7C1373D is equipped with the advanced No | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture Functional Description[1] The CY7C1371D/CY7C1373D is a 3.3V, 512K x 36/1 Mbit x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1371D/ CY7C1373D is equipped with the advanced No | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture Functional Description[1] The CY7C1371D/CY7C1373D is a 3.3V, 512K x 36/1 Mbit x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1371D/ CY7C1373D is equipped with the advanced No | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture Functional Description[1] The CY7C1371D/CY7C1373D is a 3.3V, 512K x 36/1 Mbit x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1371D/ CY7C1373D is equipped with the advanced No | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture Functional Description[1] The CY7C1371D/CY7C1373D is a 3.3V, 512K x 36/1 Mbit x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1371D/ CY7C1373D is equipped with the advanced No | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture Functional Description[1] The CY7C1371D/CY7C1373D is a 3.3V, 512K x 36/1 Mbit x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1371D/ CY7C1373D is equipped with the advanced No | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture Functional Description[1] The CY7C1371D/CY7C1373D is a 3.3V, 512K x 36/1 Mbit x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1371D/ CY7C1373D is equipped with the advanced No | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture Functional Description[1] The CY7C1371D/CY7C1373D is a 3.3V, 512K x 36/1 Mbit x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1371D/ CY7C1373D is equipped with the advanced No | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL??Architecture 文件：1.01162 Mbytes Page：29 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit (512 K 횞 36/1 M 횞 18) Flow-Through SRAM with NoBL??Architecture 文件：1.07276 Mbytes Page：37 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit (512 K 횞 36/1 M 횞 18) Flow-Through SRAM with NoBL??Architecture 文件：1.07276 Mbytes Page：37 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL??Architecture 文件：1.01162 Mbytes Page：29 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
封装/外壳：100-LQFP 包装：托盘托盘 描述：IC SRAM 18MBIT PARALLEL 100TQFP 集成电路（IC） 存储器 | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit (512 K 횞 36/1 M 횞 18) Flow-Through SRAM with NoBL??Architecture 文件：1.07276 Mbytes Page：37 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
封装/外壳：100-LQFP 包装：托盘托盘 描述：IC SRAM 18MBIT PARALLEL 100TQFP 集成电路（IC） 存储器 | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL??Architecture 文件：1.01162 Mbytes Page：29 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL??Architecture 文件：1.01162 Mbytes Page：29 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL??Architecture 文件：1.01162 Mbytes Page：29 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL??Architecture 文件：1.01162 Mbytes Page：29 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL??Architecture 文件：1.01162 Mbytes Page：29 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL??Architecture 文件：1.01162 Mbytes Page：29 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL??Architecture 文件：1.01162 Mbytes Page：29 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL??Architecture 文件：1.01162 Mbytes Page：29 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL??Architecture 文件：1.01162 Mbytes Page：29 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL??Architecture 文件：1.01162 Mbytes Page：29 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit (512 K 횞 36/1 M 횞 18) Flow-Through SRAM with NoBL??Architecture 文件：1.07276 Mbytes Page：37 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL??Architecture 文件：1.01162 Mbytes Page：29 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit (512 K 횞 36/1 M 횞 18) Flow-Through SRAM with NoBL??Architecture 文件：1.07276 Mbytes Page：37 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL??Architecture 文件：1.01162 Mbytes Page：29 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL??Architecture 文件：1.01162 Mbytes Page：29 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL??Architecture 文件：1.01162 Mbytes Page：29 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL??Architecture 文件：1.01162 Mbytes Page：29 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL??Architecture 文件：1.01162 Mbytes Page：29 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL??Architecture 文件：1.01162 Mbytes Page：29 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL??Architecture 文件：1.01162 Mbytes Page：29 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL??Architecture 文件：1.01162 Mbytes Page：29 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL??Architecture 文件：444.2 Kbytes Page：28 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL??Architecture 文件：444.2 Kbytes Page：28 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL??Architecture 文件：444.2 Kbytes Page：28 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL??Architecture 文件：444.2 Kbytes Page：28 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL??Architecture 文件：444.2 Kbytes Page：28 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL??Architecture 文件：444.2 Kbytes Page：28 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL??Architecture 文件：444.2 Kbytes Page：28 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL??Architecture 文件：444.2 Kbytes Page：28 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL??Architecture 文件：444.2 Kbytes Page：28 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL??Architecture 文件：444.2 Kbytes Page：28 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | |
CY7C1371D产品属性
- 类型
描述
- 型号
CY7C1371D
- 功能描述
静态随机存取存储器 512Kx36 3.3V NoBL Sync FT 静态随机存取存储器 COM
- RoHS
否
- 制造商
Cypress Semiconductor
- 存储容量
16 Mbit
- 组织
1 M x 16
- 访问时间
55 ns
- 电源电压-最大
3.6 V
- 电源电压-最小
2.2 V
- 最大工作电流
22 uA
- 最大工作温度
+ 85 C
- 最小工作温度
- 40 C
- 安装风格
SMD/SMT
- 封装/箱体
TSOP-48
- 封装
Tray
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
Cypress(赛普拉斯) |
24+ |
NA/ |
8735 |
原厂直销,现货供应,账期支持! |
|||
CY |
23+ |
NA |
2005 |
专业电子元器件供应链正迈科技特价代理特价，原装元器件供应，支持开发样品 |
|||
CYPRESS |
20+ |
QFP |
500 |
样品可出,优势库存欢迎实单 |
|||
Cypress(赛普拉斯) |
23+ |
NA |
20094 |
正纳10年以上分销经验原装进口正品做服务做口碑有支持 |
|||
CYPRESS/赛普拉斯 |
23+ |
QFP |
98900 |
原厂原装正品现货!! |
|||
CYPRESS/赛普拉斯 |
2450+ |
QFP |
8850 |
只做原装正品假一赔十为客户做到零风险!! |
|||
CYPRESS |
原厂封装 |
9800 |
原装进口公司现货假一赔百 |
||||
CYPRESS |
25+23+ |
QFP |
24140 |
绝对原装正品全新进口深圳现货 |
|||
CYPRESS/赛普拉斯 |
23+ |
QFP-100 |
3000 |
一级代理原厂VIP渠道,专注军工、汽车、医疗、工业、 |
|||
CYPRESS/赛普拉斯 |
2223+ |
QFP |
26800 |
只做原装正品假一赔十为客户做到零风险 |
CY7C1371D芯片相关品牌
CY7C1371D规格书下载地址
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- CY7C136E-25NXC
- CY7C136E-25JXI
- CY7C136E-25JXC
- CY7C136AE-55NXI
- CY7C136AE-55JXI
- CY7C136
- CY7C135
- CY7C133
- CY7C132
- CY7C131
- CY7C130
- CY7C129
- CY7C109
- CY7C107
- CY7C057
- CY7C038
- CY7C037
- CY7C028
- CY7C027
- CY7C025
- CY7C024
- CY7C019
- CY7C018
- CY7C016
- CY7C009
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