256K x 36/512K x 18 Pipelined SRAM

Functional Description The Cypress Synchronous Burst SRAM family employs high-speed, low power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high valued resistors. Features • Fast access times: 2.5 ns

256K x 36/512K x 18 Pipelined SRAM

Functional Description The Cypress Synchronous Burst SRAM family employs high-speed, low power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high valued resistors. Features • Fast access times: 2.5 ns

256K x 36/512K x 18 Pipelined SRAM

Functional Description The Cypress Synchronous Burst SRAM family employs high-speed, low power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high valued resistors. Features • Fast access times: 2.5 ns

256K x 36/512K x 18 Pipelined SRAM

Functional Description The Cypress Synchronous Burst SRAM family employs high-speed, low power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high valued resistors. Features • Fast access times: 2.5 ns

256K x 36/512K x 18 Pipelined SRAM

Functional Description The Cypress Synchronous Burst SRAM family employs high-speed, low power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high valued resistors. Features • Fast access times: 2.5 ns

256K x 36/512K x 18 Pipelined SRAM

Functional Description The Cypress Synchronous Burst SRAM family employs high-speed, low power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high valued resistors. Features • Fast access times: 2.5 ns

256K x 36/512K x 18 Pipelined SRAM

Functional Description The Cypress Synchronous Burst SRAM family employs high-speed, low power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high valued resistors. Features • Fast access times: 2.5 ns

256K x 36/512K x 18 Pipelined SRAM

Functional Description The Cypress Synchronous Burst SRAM family employs high-speed, low power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high valued resistors. Features • Fast access times: 2.5 ns

256K x 36/512K x 18 Pipelined SRAM

Functional Description The Cypress Synchronous Burst SRAM family employs high-speed, low power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high valued resistors. Features • Fast access times: 2.5 ns

256K x 36/512K x 18 Pipelined SRAM

Functional Description The Cypress Synchronous Burst SRAM family employs high-speed, low power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high valued resistors. Features • Fast access times: 2.5 ns

256K x 36/512K x 18 Pipelined SRAM

Functional Description The Cypress Synchronous Burst SRAM family employs high-speed, low power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high valued resistors. Features • Fast access times: 2.5 ns

256K x 36/512K x 18 Pipelined SRAM

Functional Description The Cypress Synchronous Burst SRAM family employs high-speed, low power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high valued resistors. Features • Fast access times: 2.5 ns

256K x 36/512K x 18 Pipelined SRAM

Functional Description The Cypress Synchronous Burst SRAM family employs high-speed, low power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high valued resistors. Features • Fast access times: 2.5 ns

9-Mb (256K x 36/512K x 18) Pipelined DCD Sync SRAM

文件：550.63 Kbytes Page：32 Pages

9-Mbit (256K x 36/512K x 18) Pipelined DCD Sync SRAM

文件：549.21 Kbytes Page：29 Pages

9-Mbit (256K x 36/512K x 18) Pipelined DCD Sync SRAM

文件：458.12 Kbytes Page：27 Pages