9-Mbit (256K x 36/512K x 18) Pipelined SRAM

Functional Description The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock

9-Mbit (256K x 36/512K x 18) Pipelined SRAM

文件：521.48 Kbytes Page：31 Pages

9-Mbit (256K x 36/512K x 18) Pipelined SRAM

Functional Description The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock

9-Mbit (256K x 36/512K x 18) Pipelined SRAM

Functional Description The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock

9-Mbit (256K x 36/512K x 18) Pipelined SRAM

文件：521.48 Kbytes Page：31 Pages

9-Mbit (256 K 횞 36/512 K 횞 18) Pipelined SRAM

文件：1.17908 Mbytes Page：37 Pages

9-Mbit (256K x 36/512K x 18) Pipelined SRAM

文件：521.48 Kbytes Page：31 Pages