型号 功能描述 生产厂家 企业 LOGO 操作
CY7C1354B

9-Mb (256K x 36/512K x 18) Pipelined SRAM with NoBL Architecture

Functional Description The CY7C1354B and CY7C1356B are 3.3V, 256K x 36 and 512K x 18 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1354B and CY7C1356B

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mb (256K x 36/512K x 18) Pipelined SRAM with NoBL Architecture

Functional Description The CY7C1354B and CY7C1356B are 3.3V, 256K x 36 and 512K x 18 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1354B and CY7C1356B

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mb (256K x 36/512K x 18) Pipelined SRAM with NoBL Architecture

Functional Description The CY7C1354B and CY7C1356B are 3.3V, 256K x 36 and 512K x 18 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1354B and CY7C1356B

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mb (256K x 36/512K x 18) Pipelined SRAM with NoBL Architecture

Functional Description The CY7C1354B and CY7C1356B are 3.3V, 256K x 36 and 512K x 18 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1354B and CY7C1356B

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mb (256K x 36/512K x 18) Pipelined SRAM with NoBL Architecture

Functional Description The CY7C1354B and CY7C1356B are 3.3V, 256K x 36 and 512K x 18 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1354B and CY7C1356B

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mb (256K x 36/512K x 18) Pipelined SRAM with NoBL Architecture

Functional Description The CY7C1354B and CY7C1356B are 3.3V, 256K x 36 and 512K x 18 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1354B and CY7C1356B

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mb (256K x 36/512K x 18) Pipelined SRAM with NoBL Architecture

Functional Description The CY7C1354B and CY7C1356B are 3.3V, 256K x 36 and 512K x 18 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1354B and CY7C1356B

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mb (256K x 36/512K x 18) Pipelined SRAM with NoBL Architecture

Functional Description The CY7C1354B and CY7C1356B are 3.3V, 256K x 36 and 512K x 18 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1354B and CY7C1356B

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mb (256K x 36/512K x 18) Pipelined SRAM with NoBL Architecture

Functional Description The CY7C1354B and CY7C1356B are 3.3V, 256K x 36 and 512K x 18 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1354B and CY7C1356B

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mb (256K x 36/512K x 18) Pipelined SRAM with NoBL Architecture

Functional Description The CY7C1354B and CY7C1356B are 3.3V, 256K x 36 and 512K x 18 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1354B and CY7C1356B

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mb (256K x 36/512K x 18) Pipelined SRAM with NoBL Architecture

Functional Description The CY7C1354B and CY7C1356B are 3.3V, 256K x 36 and 512K x 18 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1354B and CY7C1356B

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mb (256K x 36/512K x 18) Pipelined SRAM with NoBL Architecture

Functional Description The CY7C1354B and CY7C1356B are 3.3V, 256K x 36 and 512K x 18 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1354B and CY7C1356B

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mb (256K x 36/512K x 18) Pipelined SRAM with NoBL Architecture

Functional Description The CY7C1354B and CY7C1356B are 3.3V, 256K x 36 and 512K x 18 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1354B and CY7C1356B

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mb (256K x 36/512K x 18) Pipelined SRAM with NoBL Architecture

Functional Description The CY7C1354B and CY7C1356B are 3.3V, 256K x 36 and 512K x 18 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1354B and CY7C1356B

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mb (256K x 36/512K x 18) Pipelined SRAM with NoBL Architecture

Functional Description The CY7C1354B and CY7C1356B are 3.3V, 256K x 36 and 512K x 18 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1354B and CY7C1356B

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mb (256K x 36/512K x 18) Pipelined SRAM with NoBL Architecture

Functional Description The CY7C1354B and CY7C1356B are 3.3V, 256K x 36 and 512K x 18 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1354B and CY7C1356B

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mb (256K x 36/512K x 18) Pipelined SRAM with NoBL Architecture

Functional Description The CY7C1354B and CY7C1356B are 3.3V, 256K x 36 and 512K x 18 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1354B and CY7C1356B

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mb (256K x 36/512K x 18) Pipelined SRAM with NoBL Architecture

Functional Description The CY7C1354B and CY7C1356B are 3.3V, 256K x 36 and 512K x 18 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1354B and CY7C1356B

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mb (256K x 36/512K x 18) Pipelined SRAM with NoBL Architecture

Functional Description The CY7C1354B and CY7C1356B are 3.3V, 256K x 36 and 512K x 18 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1354B and CY7C1356B

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

256K x 36/512K x 18 Pipelined SRAM with NoBL??Architecture

Functional Description The CY7C1354BV25 and CY7C1356BV25 are 2.5V, 256K x 36 and 512K x 18 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1354BV25 and C

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

256K x 36/512K x 18 Pipelined SRAM with NoBL??Architecture

Functional Description The CY7C1354BV25 and CY7C1356BV25 are 2.5V, 256K x 36 and 512K x 18 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1354BV25 and C

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

256K x 36/512K x 18 Pipelined SRAM with NoBL??Architecture

Functional Description The CY7C1354BV25 and CY7C1356BV25 are 2.5V, 256K x 36 and 512K x 18 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1354BV25 and C

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

256K x 36/512K x 18 Pipelined SRAM with NoBL??Architecture

Functional Description The CY7C1354BV25 and CY7C1356BV25 are 2.5V, 256K x 36 and 512K x 18 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1354BV25 and C

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

封装/外壳:119-BGA 包装:管件 描述:IC SRAM 9MBIT PARALLEL 119PBGA 集成电路(IC) 存储器

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

256K x 36/512K x 18 Pipelined SRAM with NoBL™ Architecture

Infineon

英飞凌

256K x 36/512K x 18 Pipelined SRAM with NoBL Architecture

Functional Description The CY7C1354A and CY7C1356A SRAMs are designed to eliminate dead cycles when transitioning from Read to Write or vice versa. These SRAMs are optimized for 100 bus utilization and achieve Zero Bus Latency™ (ZBL™)/No Bus Latency™ (NoBL™). They integrate 262,144 × 36 and 524

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

256K x 36/512K x 18 Pipelined SRAM with NoBL??Architecture

文件:402.54 Kbytes Page:28 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mbit (256 K 횞 36/512 K 횞 18) Pipelined SRAM with NoBL??Architecture

文件:1.11285 Mbytes Page:32 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL??Architecture

文件:516.1 Kbytes Page:28 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1354B产品属性

  • 类型

    描述

  • 型号

    CY7C1354B

  • 制造商

    Cypress Semiconductor

更新时间:2025-10-20 22:59:00
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
CYPRESS(赛普拉斯)
24+
LQFP100
7350
现货供应,当天可交货!免费送样,原厂技术支持!!!
CYPRESS/赛普拉斯
24+
NA/
4332
原装现货,当天可交货,原型号开票
CYPRESS
2016+
TQFP
9000
只做原装,假一罚十,公司可开17%增值税发票!
CYPRESS
24+
TQFP-100
8000
只做自己库存,全新原装进口正品假一赔百,可开13%增
CYPRESS/赛普拉斯
25+
QFP100
54658
百分百原装现货 实单必成
CYPRESS/赛普拉斯
22+
QFP100
100000
代理渠道/只做原装/可含税
CYPRESS/赛普拉斯
24+
QFP
880000
明嘉莱只做原装正品现货
CY
24+
QFP
20000
全新原厂原装,进口正品现货,正规渠道可含税!!
Cypress
0336+
QFP100
1435
一级代理,专注军工、汽车、医疗、工业、新能源、电力
CYPRESS
20+
QFP
500
样品可出,优势库存欢迎实单

CY7C1354B数据表相关新闻