型号 功能描述 生产厂家&企业 LOGO 操作
CY7C1354B

9-Mb(256Kx36/512Kx18)PipelinedSRAMwithNoBLArchitecture

FunctionalDescription TheCY7C1354BandCY7C1356Bare3.3V,256Kx36and512Kx18SynchronouspipelinedburstSRAMswithNoBusLatency™(NoBL)logic,respectively.Theyaredesignedtosupportunlimitedtrueback-to-backRead/Writeoperationswithnowaitstates.TheCY7C1354BandCY7C1356B

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

9-Mb(256Kx36/512Kx18)PipelinedSRAMwithNoBLArchitecture

FunctionalDescription TheCY7C1354BandCY7C1356Bare3.3V,256Kx36and512Kx18SynchronouspipelinedburstSRAMswithNoBusLatency™(NoBL)logic,respectively.Theyaredesignedtosupportunlimitedtrueback-to-backRead/Writeoperationswithnowaitstates.TheCY7C1354BandCY7C1356B

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

9-Mb(256Kx36/512Kx18)PipelinedSRAMwithNoBLArchitecture

FunctionalDescription TheCY7C1354BandCY7C1356Bare3.3V,256Kx36and512Kx18SynchronouspipelinedburstSRAMswithNoBusLatency™(NoBL)logic,respectively.Theyaredesignedtosupportunlimitedtrueback-to-backRead/Writeoperationswithnowaitstates.TheCY7C1354BandCY7C1356B

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

9-Mb(256Kx36/512Kx18)PipelinedSRAMwithNoBLArchitecture

FunctionalDescription TheCY7C1354BandCY7C1356Bare3.3V,256Kx36and512Kx18SynchronouspipelinedburstSRAMswithNoBusLatency™(NoBL)logic,respectively.Theyaredesignedtosupportunlimitedtrueback-to-backRead/Writeoperationswithnowaitstates.TheCY7C1354BandCY7C1356B

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

9-Mb(256Kx36/512Kx18)PipelinedSRAMwithNoBLArchitecture

FunctionalDescription TheCY7C1354BandCY7C1356Bare3.3V,256Kx36and512Kx18SynchronouspipelinedburstSRAMswithNoBusLatency™(NoBL)logic,respectively.Theyaredesignedtosupportunlimitedtrueback-to-backRead/Writeoperationswithnowaitstates.TheCY7C1354BandCY7C1356B

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

9-Mb(256Kx36/512Kx18)PipelinedSRAMwithNoBLArchitecture

FunctionalDescription TheCY7C1354BandCY7C1356Bare3.3V,256Kx36and512Kx18SynchronouspipelinedburstSRAMswithNoBusLatency™(NoBL)logic,respectively.Theyaredesignedtosupportunlimitedtrueback-to-backRead/Writeoperationswithnowaitstates.TheCY7C1354BandCY7C1356B

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

9-Mb(256Kx36/512Kx18)PipelinedSRAMwithNoBLArchitecture

FunctionalDescription TheCY7C1354BandCY7C1356Bare3.3V,256Kx36and512Kx18SynchronouspipelinedburstSRAMswithNoBusLatency™(NoBL)logic,respectively.Theyaredesignedtosupportunlimitedtrueback-to-backRead/Writeoperationswithnowaitstates.TheCY7C1354BandCY7C1356B

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

9-Mb(256Kx36/512Kx18)PipelinedSRAMwithNoBLArchitecture

FunctionalDescription TheCY7C1354BandCY7C1356Bare3.3V,256Kx36and512Kx18SynchronouspipelinedburstSRAMswithNoBusLatency™(NoBL)logic,respectively.Theyaredesignedtosupportunlimitedtrueback-to-backRead/Writeoperationswithnowaitstates.TheCY7C1354BandCY7C1356B

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

9-Mb(256Kx36/512Kx18)PipelinedSRAMwithNoBLArchitecture

FunctionalDescription TheCY7C1354BandCY7C1356Bare3.3V,256Kx36and512Kx18SynchronouspipelinedburstSRAMswithNoBusLatency™(NoBL)logic,respectively.Theyaredesignedtosupportunlimitedtrueback-to-backRead/Writeoperationswithnowaitstates.TheCY7C1354BandCY7C1356B

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

9-Mb(256Kx36/512Kx18)PipelinedSRAMwithNoBLArchitecture

FunctionalDescription TheCY7C1354BandCY7C1356Bare3.3V,256Kx36and512Kx18SynchronouspipelinedburstSRAMswithNoBusLatency™(NoBL)logic,respectively.Theyaredesignedtosupportunlimitedtrueback-to-backRead/Writeoperationswithnowaitstates.TheCY7C1354BandCY7C1356B

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

9-Mb(256Kx36/512Kx18)PipelinedSRAMwithNoBLArchitecture

FunctionalDescription TheCY7C1354BandCY7C1356Bare3.3V,256Kx36and512Kx18SynchronouspipelinedburstSRAMswithNoBusLatency™(NoBL)logic,respectively.Theyaredesignedtosupportunlimitedtrueback-to-backRead/Writeoperationswithnowaitstates.TheCY7C1354BandCY7C1356B

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

9-Mb(256Kx36/512Kx18)PipelinedSRAMwithNoBLArchitecture

FunctionalDescription TheCY7C1354BandCY7C1356Bare3.3V,256Kx36and512Kx18SynchronouspipelinedburstSRAMswithNoBusLatency™(NoBL)logic,respectively.Theyaredesignedtosupportunlimitedtrueback-to-backRead/Writeoperationswithnowaitstates.TheCY7C1354BandCY7C1356B

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

9-Mb(256Kx36/512Kx18)PipelinedSRAMwithNoBLArchitecture

FunctionalDescription TheCY7C1354BandCY7C1356Bare3.3V,256Kx36and512Kx18SynchronouspipelinedburstSRAMswithNoBusLatency™(NoBL)logic,respectively.Theyaredesignedtosupportunlimitedtrueback-to-backRead/Writeoperationswithnowaitstates.TheCY7C1354BandCY7C1356B

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

9-Mb(256Kx36/512Kx18)PipelinedSRAMwithNoBLArchitecture

FunctionalDescription TheCY7C1354BandCY7C1356Bare3.3V,256Kx36and512Kx18SynchronouspipelinedburstSRAMswithNoBusLatency™(NoBL)logic,respectively.Theyaredesignedtosupportunlimitedtrueback-to-backRead/Writeoperationswithnowaitstates.TheCY7C1354BandCY7C1356B

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

9-Mb(256Kx36/512Kx18)PipelinedSRAMwithNoBLArchitecture

FunctionalDescription TheCY7C1354BandCY7C1356Bare3.3V,256Kx36and512Kx18SynchronouspipelinedburstSRAMswithNoBusLatency™(NoBL)logic,respectively.Theyaredesignedtosupportunlimitedtrueback-to-backRead/Writeoperationswithnowaitstates.TheCY7C1354BandCY7C1356B

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

9-Mb(256Kx36/512Kx18)PipelinedSRAMwithNoBLArchitecture

FunctionalDescription TheCY7C1354BandCY7C1356Bare3.3V,256Kx36and512Kx18SynchronouspipelinedburstSRAMswithNoBusLatency™(NoBL)logic,respectively.Theyaredesignedtosupportunlimitedtrueback-to-backRead/Writeoperationswithnowaitstates.TheCY7C1354BandCY7C1356B

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

9-Mb(256Kx36/512Kx18)PipelinedSRAMwithNoBLArchitecture

FunctionalDescription TheCY7C1354BandCY7C1356Bare3.3V,256Kx36and512Kx18SynchronouspipelinedburstSRAMswithNoBusLatency™(NoBL)logic,respectively.Theyaredesignedtosupportunlimitedtrueback-to-backRead/Writeoperationswithnowaitstates.TheCY7C1354BandCY7C1356B

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

9-Mb(256Kx36/512Kx18)PipelinedSRAMwithNoBLArchitecture

FunctionalDescription TheCY7C1354BandCY7C1356Bare3.3V,256Kx36and512Kx18SynchronouspipelinedburstSRAMswithNoBusLatency™(NoBL)logic,respectively.Theyaredesignedtosupportunlimitedtrueback-to-backRead/Writeoperationswithnowaitstates.TheCY7C1354BandCY7C1356B

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

9-Mb(256Kx36/512Kx18)PipelinedSRAMwithNoBLArchitecture

FunctionalDescription TheCY7C1354BandCY7C1356Bare3.3V,256Kx36and512Kx18SynchronouspipelinedburstSRAMswithNoBusLatency™(NoBL)logic,respectively.Theyaredesignedtosupportunlimitedtrueback-to-backRead/Writeoperationswithnowaitstates.TheCY7C1354BandCY7C1356B

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

256Kx36/512Kx18PipelinedSRAMwithNoBL??Architecture

FunctionalDescription TheCY7C1354BV25andCY7C1356BV25are2.5V,256Kx36and512Kx18SynchronouspipelinedburstSRAMswithNoBusLatency™(NoBL)logic,respectively.Theyaredesignedtosupportunlimitedtrueback-to-backRead/Writeoperationswithnowaitstates.TheCY7C1354BV25andC

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

256Kx36/512Kx18PipelinedSRAMwithNoBL??Architecture

FunctionalDescription TheCY7C1354BV25andCY7C1356BV25are2.5V,256Kx36and512Kx18SynchronouspipelinedburstSRAMswithNoBusLatency™(NoBL)logic,respectively.Theyaredesignedtosupportunlimitedtrueback-to-backRead/Writeoperationswithnowaitstates.TheCY7C1354BV25andC

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

256Kx36/512Kx18PipelinedSRAMwithNoBL??Architecture

FunctionalDescription TheCY7C1354BV25andCY7C1356BV25are2.5V,256Kx36and512Kx18SynchronouspipelinedburstSRAMswithNoBusLatency™(NoBL)logic,respectively.Theyaredesignedtosupportunlimitedtrueback-to-backRead/Writeoperationswithnowaitstates.TheCY7C1354BV25andC

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

256Kx36/512Kx18PipelinedSRAMwithNoBL??Architecture

FunctionalDescription TheCY7C1354BV25andCY7C1356BV25are2.5V,256Kx36and512Kx18SynchronouspipelinedburstSRAMswithNoBusLatency™(NoBL)logic,respectively.Theyaredesignedtosupportunlimitedtrueback-to-backRead/Writeoperationswithnowaitstates.TheCY7C1354BV25andC

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

封装/外壳:119-BGA 包装:管件 描述:IC SRAM 9MBIT PARALLEL 119PBGA 集成电路(IC) 存储器

CYP

Cypress Semiconductor Corp

CYP

256Kx36/512Kx18PipelinedSRAMwithNoBLArchitecture

FunctionalDescription TheCY7C1354AandCY7C1356ASRAMsaredesignedtoeliminatedeadcycleswhentransitioningfromReadtoWriteorviceversa.TheseSRAMsareoptimizedfor100busutilizationandachieveZeroBusLatency™(ZBL™)/NoBusLatency™(NoBL™).Theyintegrate262,144×36and524

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

256Kx36/512Kx18PipelinedSRAMwithNoBL??Architecture

文件:402.54 Kbytes Page:28 Pages

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

9-Mbit(256K횞36/512K횞18)PipelinedSRAMwithNoBL??Architecture

文件:1.11285 Mbytes Page:32 Pages

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

9-Mbit(256Kx36/512Kx18)PipelinedSRAMwithNoBL??Architecture

文件:516.1 Kbytes Page:28 Pages

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

CY7C1354B产品属性

  • 类型

    描述

  • 型号

    CY7C1354B

  • 制造商

    Cypress Semiconductor

更新时间:2024-6-21 22:30:00
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
CYPRESS
2019+
TQFP-100
8000
只做自己库存,全新原装进口正品假一赔百,可开13%增
CYPRESS/赛普拉斯
22+
QFP100
100000
代理渠道/只做原装/可含税
CYPRESS/赛普拉斯
24+
QFP
880000
明嘉莱只做原装正品现货
CY
23+
QFP
20000
原厂原装正品现货
CYPRESS
23+
QFP
20000
原装进口ICMCUSOCMOS等知名国内外品牌只做原装全
CYPRESS
23+
TQFP
1200
绝对现货库存
Cypress
0336+
QFP100
1435
一级代理,专注军工、汽车、医疗、工业、新能源、电力
CYPRESS/赛普拉斯
18+
QFP
30633
全新原装现货,可出样品,可开增值税发票
CYPRESS
2016+
TQFP
9000
只做原装,假一罚十,公司可开17%增值税发票!
CYPRESS/赛普拉斯
20+
BGA
9850
只做原装正品假一赔十为客户做到零风险!!

CY7C1354B芯片相关品牌

  • API
  • APITECH
  • BOARDCOM
  • crydom
  • Hitachi
  • IDT
  • LUGUANG
  • MOLEX4
  • NEC
  • POWEREX
  • SILABS
  • SUPERWORLD

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