4-Mbit (128 K x 36) Pipelined Sync SRAM

文件：567.9 Kbytes Page：26 Pages

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i

4-Mbit (128 K x 36) Pipelined Sync SRAM Asynchronous output enable

文件：808.8 Kbytes Page：24 Pages

4-Mbit (128 K 횞 36) Pipelined Sync SRAM

文件：538.13 Kbytes Page：25 Pages

4-Mbit (128 K x 36) Pipelined Sync SRAM

文件：567.9 Kbytes Page：26 Pages

封装/外壳：100-LQFP 包装：卷带（TR） 描述：IC SRAM 4.5MBIT PARALLEL 100TQFP 集成电路（IC） 存储器

4-Mbit (128 K x 36) Pipelined Sync SRAM Asynchronous output enable

文件：808.8 Kbytes Page：24 Pages

4-Mbit (128 K x 36) Pipelined Sync SRAM

文件：567.9 Kbytes Page：26 Pages

4-Mbit (128 K 횞 36) Pipelined Sync SRAM

文件：538.13 Kbytes Page：25 Pages

封装/外壳：119-BGA 包装：卷带（TR） 描述：IC SRAM 4.5MBIT PARALLEL 119PBGA 集成电路（IC） 存储器