4-Mbit (128 K x 36) Flow-Through Sync SRAM

文件：771.78 Kbytes Page：24 Pages

4-Mbit (128K x 36) Flow-Through Sync SRAM

Functional Description[1] The CY7C1345G is a 131,072 x 36 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increm

4-Mbit (128K x 36) Flow-Through Sync SRAM

Functional Description[1] The CY7C1345G is a 131,072 x 36 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increm

4-Mbit (128K x 36) Flow-Through Sync SRAM

Functional Description[1] The CY7C1345G is a 131,072 x 36 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increm

4-Mbit (128K x 36) Flow-Through Sync SRAM

Functional Description[1] The CY7C1345G is a 131,072 x 36 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increm

4-Mbit (128K x 36) Flow-Through Sync SRAM

Functional Description[1] The CY7C1345G is a 131,072 x 36 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increm

4-Mbit (128K x 36) Flow-Through Sync SRAM

Functional Description[1] The CY7C1345G is a 131,072 x 36 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increm

4-Mbit (128K x 36) Flow Through Sync SRAM

文件：767.49 Kbytes Page：20 Pages

4-Mbit (128K x 36) Flow Through Sync SRAM

文件：767.49 Kbytes Page：20 Pages

4-Mbit (128K x 36) Flow Through Sync SRAM

文件：767.49 Kbytes Page：20 Pages

4-Mbit (128K x 36) Flow Through Sync SRAM

文件：767.49 Kbytes Page：20 Pages

4-Mbit (128K x 36) Flow Through Sync SRAM

文件：767.49 Kbytes Page：20 Pages

4-Mbit (128K x 36) Flow Through Sync SRAM

文件：767.49 Kbytes Page：20 Pages