2-Mbit (64K x 36) Flow-Through Sync SRAM

Functional Description[1] The CY7C1344F is a 65,536 x 36 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter captures the first address in a burst and increme

2-Mbit (64K x 36) Flow-Through Sync SRAM

Functional Description[1] The CY7C1344F is a 65,536 x 36 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter captures the first address in a burst and increme

2-Mbit (64K x 36) Flow-Through Sync SRAM

2-Mbit (64K x 36) Flow-Through Sync SRAM

Functional Description[1] The CY7C1344H is a 64K x 36 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments