2-Mbit (64K x 32) Pipelined Sync SRAM

Features • Registered inputs and outputs for pipelined operation • 64K × 32 common I/O architecture • 3.3V core power supply • 2.5V/3.3V I/O operation • Fast clock-to-output times — 3.5 ns (for 166-MHz device) — 4.0 ns (for 133-MHz device) • Provide high-performance 3-1-1-1 access ra

2-Mbit (64 K x 32) Pipelined Sync SRAM 2.5 V/3.3 V I/O operation

文件：618.5 Kbytes Page：20 Pages

2-Mbit (64K x 32) Pipelined Sync SRAM

2-Mbit (64K x 32) Pipelined Sync SRAM

Features • Registered inputs and outputs for pipelined operation • 64K × 32 common I/O architecture • 3.3V core power supply • 2.5V/3.3V I/O operation • Fast clock-to-output times — 3.5 ns (for 166-MHz device) — 4.0 ns (for 133-MHz device) • Provide high-performance 3-1-1-1 access ra

2-Mbit (64K x 32) Pipelined Sync SRAM

Features • Registered inputs and outputs for pipelined operation • 64K × 32 common I/O architecture • 3.3V core power supply • 2.5V/3.3V I/O operation • Fast clock-to-output times — 3.5 ns (for 166-MHz device) — 4.0 ns (for 133-MHz device) • Provide high-performance 3-1-1-1 access ra

2-Mbit (64K x 32) Pipelined Sync SRAM

Features • Registered inputs and outputs for pipelined operation • 64K × 32 common I/O architecture • 3.3V core power supply • 2.5V/3.3V I/O operation • Fast clock-to-output times — 3.5 ns (for 166-MHz device) — 4.0 ns (for 133-MHz device) • Provide high-performance 3-1-1-1 access ra

2-Mbit (64K x 32) Pipelined Sync SRAM

Features • Registered inputs and outputs for pipelined operation • 64K × 32 common I/O architecture • 3.3V core power supply • 2.5V/3.3V I/O operation • Fast clock-to-output times — 3.5 ns (for 166-MHz device) — 4.0 ns (for 133-MHz device) • Provide high-performance 3-1-1-1 access ra

2-Mbit (64 K x 32) Pipelined Sync SRAM 2.5 V/3.3 V I/O operation

文件：618.5 Kbytes Page：20 Pages

2-Mbit (64 K x 32) Pipelined Sync SRAM 2.5 V/3.3 V I/O operation

文件：618.5 Kbytes Page：20 Pages

封装/外壳：100-LQFP 包装：托盘 描述：IC SRAM 2MBIT PARALLEL 100TQFP 集成电路（IC） 存储器

同步 SRAM

IC SRAM 2M PARALLEL 100TQFP

封装/外壳：100-LQFP 包装：卷带（TR） 描述：IC SRAM 2MBIT PARALLEL 100TQFP 集成电路（IC） 存储器

64K x 32 Synchronous-Pipelined Cache RAM

Features • Supports 133-MHz bus for Pentium® and PowerPC™ operations with zero wait states • Fully registered inputs and outputs for pipelined operation • 64K x 32 common I/O architecture • Single 3.3V power supply • Fast clock-to-output times — 4.2 ns (for 133-MHz device) — 5.5 n

64K x 32 Synchronous-Pipelined Cache RAM

Features • Supports 133-MHz bus for Pentium® and PowerPC operations with zero wait states • Fully registered inputs and outputs for pipelined operation • 64K x 32 common I/O architecture • Single 3.3V power supply • Fast clock-to-output times — 4.2 ns (for 133-MHz device) — 5.5 n

2-Mb (64K x 32) Pipelined Sync SRAM

Features • Registered inputs and outputs for pipelined operation • 64K × 32 common I/O architecture • 3.3V core power supply • 2.5V I/O operation • Fast clock-to-output times — 3.5 ns (for 166-MHz device) — 4.0 ns (for 133-MHz device) • Provide high-performance 3-1-1-1 access rate •