2-Mbit (128K x 18) Flow-Through Sync SRAM

Functional Description[1] The CY7C1324H is a 128K x 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increment

2-Mbit (128K x 18) Flow-Through Sync SRAM

2-Mbit (128K x 18) Flow-Through Sync SRAM

Functional Description[1] The CY7C1324H is a 128K x 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increment

2-Mbit (128K x 18) Flow-Through Sync SRAM

Functional Description[1] The CY7C1324H is a 128K x 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increment

封装/外壳：100-LQFP 包装：卷带（TR） 描述：IC SRAM 2MBIT PARALLEL 100TQFP 集成电路（IC） 存储器

封装/外壳：100-LQFP 包装：卷带（TR） 描述：IC SRAM 2MBIT PARALLEL 100TQFP 集成电路（IC） 存储器

2-Mb (128K x 18) Flow-Through Sync SRAM

Functional Description[1] The CY7C1324F is a 131,072 x 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increm