1K x 8 Dual-Port Static Ram

Functional Description The CY7C130/CY7C131/CY7C140 and CY7C141 are high-speed CMOS 1K by 8 dual-port static RAMs. Two ports are provided permitting independent access to any location in memory. The CY7C130/ CY7C131 can be utilized as either a standalone 8-bit dual-port static RAM or as a master

1K x 8 Dual-Port Static RAM

文件：570.93 Kbytes Page：19 Pages

128K X 36 Dual I/O Dual Address Synchronous SRAM

Functional Description The CY7C1300A SRAM integrates 131,072 × 36 SRAM cells with advanced synchronous peripheral circuitry. It employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two

128K X 36 Dual I/O Dual Address Synchronous SRAM

Functional Description The CY7C1300A SRAM integrates 131,072 × 36 SRAM cells with advanced synchronous peripheral circuitry. It employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two

128K X 36 Dual I/O Dual Address Synchronous SRAM

Functional Description The CY7C1300A SRAM integrates 131,072 × 36 SRAM cells with advanced synchronous peripheral circuitry. It employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two

9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture

Functional Description The CY7C1302DV25 is a 2.5V Synchronous Pipelined SRAM equipped with QDR™ architecture. QDR architecture consists of two separate ports to access the memory array. The Read port has dedicated data outputs to support Read operations and the Write Port has dedicated data input

9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture

Functional Description The CY7C1302DV25 is a 2.5V Synchronous Pipelined SRAM equipped with QDR™ architecture. QDR architecture consists of two separate ports to access the memory array. The Read port has dedicated data outputs to support Read operations and the Write Port has dedicated data input

9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture

Functional Description The CY7C1302DV25 is a 2.5V Synchronous Pipelined SRAM equipped with QDR™ architecture. QDR architecture consists of two separate ports to access the memory array. The Read port has dedicated data outputs to support Read operations and the Write Port has dedicated data input

9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture

Functional Description The CY7C1302DV25 is a 2.5V Synchronous Pipelined SRAM equipped with QDR™ architecture. QDR architecture consists of two separate ports to access the memory array. The Read port has dedicated data outputs to support Read operations and the Write Port has dedicated data input

1K x 8 Dual-Port Static Ram

Functional Description The CY7C130/CY7C131/CY7C140 and CY7C141 are high-speed CMOS 1K by 8 dual-port static RAMs. Two ports are provided permitting independent access to any location in memory. The CY7C130/ CY7C131 can be utilized as either a standalone 8-bit dual-port static RAM or as a master

1K x 8 Dual-Port Static Ram

Functional Description The CY7C130/CY7C131/CY7C140 and CY7C141 are high-speed CMOS 1K by 8 dual-port static RAMs. Two ports are provided permitting independent access to any location in memory. The CY7C130/ CY7C131 can be utilized as either a standalone 8-bit dual-port static RAM or as a master

1K x 8 Dual-Port Static Ram

Functional Description The CY7C130/CY7C131/CY7C140 and CY7C141 are high-speed CMOS 1K by 8 dual-port static RAMs. Two ports are provided permitting independent access to any location in memory. The CY7C130/ CY7C131 can be utilized as either a standalone 8-bit dual-port static RAM or as a master

1K x 8 Dual-Port Static Ram

Functional Description The CY7C130/CY7C131/CY7C140 and CY7C141 are high-speed CMOS 1K by 8 dual-port static RAMs. Two ports are provided permitting independent access to any location in memory. The CY7C130/ CY7C131 can be utilized as either a standalone 8-bit dual-port static RAM or as a master

1K x 8 Dual-Port Static Ram

Functional Description The CY7C130/CY7C131/CY7C140 and CY7C141 are high-speed CMOS 1K by 8 dual-port static RAMs. Two ports are provided permitting independent access to any location in memory. The CY7C130/ CY7C131 can be utilized as either a standalone 8-bit dual-port static RAM or as a master

1K x 8 Dual-Port Static Ram

Functional Description The CY7C130/CY7C131/CY7C140 and CY7C141 are high-speed CMOS 1K by 8 dual-port static RAMs. Two ports are provided permitting independent access to any location in memory. The CY7C130/ CY7C131 can be utilized as either a standalone 8-bit dual-port static RAM or as a master

1K x 8 Dual-Port Static Ram

Functional Description The CY7C130/CY7C131/CY7C140 and CY7C141 are high-speed CMOS 1K by 8 dual-port static RAMs. Two ports are provided permitting independent access to any location in memory. The CY7C130/ CY7C131 can be utilized as either a standalone 8-bit dual-port static RAM or as a master

1K x 8 Dual-Port Static Ram

Functional Description The CY7C130/CY7C131/CY7C140 and CY7C141 are high-speed CMOS 1K by 8 dual-port static RAMs. Two ports are provided permitting independent access to any location in memory. The CY7C130/ CY7C131 can be utilized as either a standalone 8-bit dual-port static RAM or as a master

1K x 8 Dual-Port Static Ram

Functional Description The CY7C130/CY7C131/CY7C140 and CY7C141 are high-speed CMOS 1K by 8 dual-port static RAMs. Two ports are provided permitting independent access to any location in memory. The CY7C130/ CY7C131 can be utilized as either a standalone 8-bit dual-port static RAM or as a master

1K x 8 Dual-Port Static Ram

Functional Description The CY7C130/CY7C131/CY7C140 and CY7C141 are high-speed CMOS 1K by 8 dual-port static RAMs. Two ports are provided permitting independent access to any location in memory. The CY7C130/ CY7C131 can be utilized as either a standalone 8-bit dual-port static RAM or as a master

1K x 8 Dual-Port Static Ram

Functional Description The CY7C130/CY7C131/CY7C140 and CY7C141 are high-speed CMOS 1K by 8 dual-port static RAMs. Two ports are provided permitting independent access to any location in memory. The CY7C130/ CY7C131 can be utilized as either a standalone 8-bit dual-port static RAM or as a master

RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata

RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata This document describes the DOFF issue for QDRII/DDRII and the Output Buffer and JTAG issues for QDRI/DDRI/QDRII/DDRII. Details include trigger conditions, possible workarounds and silicon revision applicability. This document should be used to compare to th

RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata

RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata This document describes the DOFF issue for QDRII/DDRII and the Output Buffer and JTAG issues for QDRI/DDRI/QDRII/DDRII. Details include trigger conditions, possible workarounds and silicon revision applicability. This document should be used to compare to th

RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata

RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata This document describes the DOFF issue for QDRII/DDRII and the Output Buffer and JTAG issues for QDRI/DDRI/QDRII/DDRII. Details include trigger conditions, possible workarounds and silicon revision applicability. This document should be used to compare to th

1K x 8 Dual-Port Static RAM

文件：570.93 Kbytes Page：19 Pages

1 K 횞 8 Dual-Port Static RAM

文件：480.64 Kbytes Page：22 Pages

9-Mbit Burst of Two Pipelined SRAMs with QDR™ Architecture

9-Mbit Burst of Two Pipelined SRAMs with QDR??Architecture

文件：296.16 Kbytes Page：18 Pages

9-Mbit Burst of Two Pipelined SRAMs with QDR??Architecture

文件：296.16 Kbytes Page：18 Pages

9-Mbit Burst of Two Pipelined SRAMs with QDR??Architecture

文件：296.16 Kbytes Page：18 Pages

9-Mbit Burst of Two Pipelined SRAMs with QDR??Architecture

文件：296.16 Kbytes Page：18 Pages

9-Mbit Burst of Two Pipelined SRAMs with QDR??Architecture

文件：296.16 Kbytes Page：18 Pages

9-Mbit Burst of Two Pipelined SRAMs with QDR??Architecture

文件：296.16 Kbytes Page：18 Pages

9-Mbit Burst of Two Pipelined SRAMs with QDR??Architecture

文件：296.16 Kbytes Page：18 Pages

9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture

文件：386.63 Kbytes Page：18 Pages

9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture

9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture JTAG Interface

文件：713.5 Kbytes Page：25 Pages

9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture

文件：386.63 Kbytes Page：18 Pages

9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture JTAG Interface

文件：713.5 Kbytes Page：25 Pages

9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture JTAG Interface

文件：713.5 Kbytes Page：25 Pages

9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture

文件：386.63 Kbytes Page：18 Pages

9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture

文件：386.63 Kbytes Page：18 Pages

9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture

文件：386.63 Kbytes Page：18 Pages

封装/外壳：165-LBGA 包装：卷带（TR） 描述：IC SRAM 9MBIT PARALLEL 165FBGA 集成电路（IC） 存储器

9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture

文件：386.63 Kbytes Page：18 Pages

1K x 8 Dual-Port Static RAM

文件：570.93 Kbytes Page：19 Pages

1K x 8 Dual-Port Static RAM

文件：570.93 Kbytes Page：19 Pages

1K x 8 Dual-Port Static RAM

1K x 8 Dual-Port Static RAM

文件：570.93 Kbytes Page：19 Pages

1K x 8 Dual-Port Static RAM

文件：570.93 Kbytes Page：19 Pages

1K x 8 Dual-Port Static RAM

文件：570.93 Kbytes Page：19 Pages

18-Mb Burst of 2 Pipelined SRAM with QDR??Architecture

文件：479.46 Kbytes Page：20 Pages

18-Mb Burst of 2 Pipelined SRAM with QDR??Architecture

文件：479.46 Kbytes Page：20 Pages

18-Mb Burst of 2 Pipelined SRAM with QDR??Architecture

文件：479.46 Kbytes Page：20 Pages

18-Mb Burst of 2 Pipelined SRAM with QDR??Architecture

文件：479.46 Kbytes Page：20 Pages

18-Mb Burst of 2 Pipelined SRAM with QDR??Architecture

文件：479.1 Kbytes Page：19 Pages

18-Mb Burst of 2 Pipelined SRAM with QDR??Architecture

文件：479.1 Kbytes Page：19 Pages

18-Mb Burst of 2 Pipelined SRAM with QDR??Architecture

文件：479.1 Kbytes Page：19 Pages

18-Mb Burst of 2 Pipelined SRAM with QDR??Architecture

文件：479.1 Kbytes Page：19 Pages

18-Mbit Burst of 2 Pipelined SRAM with QDR??Architecture

文件：246.57 Kbytes Page：19 Pages

18-Mbit Burst of 2 Pipelined SRAM with QDR??Architecture

文件：246.57 Kbytes Page：19 Pages