1-Mbit (64K x 18) Flow-Through Sync SRAM

Functional Description[1] The CY7C1297H is a 64K x 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments

1-Mbit (64K x 18) Flow-Through Sync SRAM

1-Mbit (64K x 18) Flow-Through Sync SRAM

Functional Description[1] The CY7C1297H is a 64K x 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments

1-Mbit (64K x 18) Flow-Through Sync SRAM

Functional Description[1] The CY7C1297H is a 64K x 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments

1-Mbit (64K x 18) Flow-Through Sync SRAM

Functional Description[1] The CY7C1297H is a 64K x 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments

1-Mbit (64K x 18) Flow-Through Sync SRAM

Functional Description[1] The CY7C1297H is a 64K x 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments

封装/外壳：100-LQFP 包装：卷带（TR） 描述：IC SRAM 1MBIT PARALLEL 100TQFP 集成电路（IC） 存储器

64K X 18 Synchronous Burst SRAM

Functional Description The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced double-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors. Features • Fast access times: 9 and 10

1-Mbit (64K x 18) Flow-Through Sync SRAM

Functional Description[1] The CY7C1297F is a 131,072 x 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increm