64K x 18 Synchronous Cache RAM

Functional Description The CY7C1031 and CY7C1032 are 64K by 18 synchronous cache RAMs designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 8.5 ns. A 2-bit on-chip counter captures the first address in a burst and increments the add

64K x 18 Synchronous Cache RAM

Functional Description The CY7C1031 and CY7C1032 are 64K by 18 synchronous cache RAMs designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 8.5 ns. A 2-bit on-chip counter captures the first address in a burst and increments the add

64K x 18 Synchronous Cache RAM

Functional Description The CY7C1031 and CY7C1032 are 64K by 18 synchronous cache RAMs designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 8.5 ns. A 2-bit on-chip counter captures the first address in a burst and increments the add

64K x 18 Synchronous Cache RAM

Functional Description The CY7C1031 and CY7C1032 are 64K by 18 synchronous cache RAMs designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 8.5 ns. A 2-bit on-chip counter captures the first address in a burst and increments the add

64K x 18 Synchronous Cache RAM

Functional Description The CY7C1031 and CY7C1032 are 64K by 18 synchronous cache RAMs designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 8.5 ns. A 2-bit on-chip counter captures the first address in a burst and increments the add

64K x 18 Synchronous Cache RAM

Functional Description The CY7C1031 and CY7C1032 are 64K by 18 synchronous cache RAMs designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 8.5 ns. A 2-bit on-chip counter captures the first address in a burst and increments the add

64K x 18 Synchronous Cache RAM

Functional Description The CY7C1031 and CY7C1032 are 64K by 18 synchronous cache RAMs designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 8.5 ns. A 2-bit on-chip counter captures the first address in a burst and increments the add

32K x 18K; 10.5ns; 280mA PCI prototype board

6-Mbit (256K X 24) Static RAM

文件：300.51 Kbytes Page：8 Pages

6-Mbit (256K X 24) Static RAM

文件：443.05 Kbytes Page：9 Pages

6-Mbit (256K X 24) Static RAM

6-Mbit (256K X 24) Static RAM

文件：443.05 Kbytes Page：9 Pages

6-Mbit (256K X 24) Static RAM

文件：398.4 Kbytes Page：9 Pages

封装/外壳：119-BGA 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC SRAM 6MBIT PARALLEL 119PBGA 集成电路（IC） 存储器

6-Mbit (256K X 24) Static RAM

文件：398.4 Kbytes Page：9 Pages

Async Fast SRAMs

封装/外壳：119-BGA 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC SRAM 6MBIT PARALLEL 119PBGA 集成电路（IC） 存储器

6-Mbit (256K X 24) Static RAM

文件：300.51 Kbytes Page：8 Pages

6-Mbit (256K X 24) Static RAM

文件：443.05 Kbytes Page：9 Pages