封装/外壳：8-TSSOP（0.173"，4.40mm 宽） 包装：卷带（TR） 描述：IC CLOCK GEN FIELD PRG 8-TSSOP 集成电路（IC） 时钟发生器，PLL，频率合成器

IC CLOCK GEN FIELD PRG 8-TSSOP

Quad ISDN Echocancellation Circuit Analogue Front End Quad IEC AFE

Overview The PEB 24902 Quad IEC AFE (Quadruple ISDN Echocancellation Circuit Analogue Front End) is part of a 2B1Q or 4B3T ISDN U-transceiver chip set. Up to four lines can be accessed simultaneously by the Quad IEC AFE. The Quad IEC AFE is optimized to work in conjunction with the PEB 24901 Quad

Quad ISDN Echocancellation Circuit Analog Front End for Splitterless ADSL over ISDN

Overview The IEC-4-AFE-X Version 3.2 is part of Infineon´s chip set for a splitterless, FDD (non-overlapped) ADSL over ISDN linecard based on GEMINAX MAX according to Ref [3.], chapter 4.2.2 of Ref [5.], Annex B of Ref [6.] / Ref [7.], and Ref [8.]. Figure 1 shows the basic architecture of an in

Quad ISDN Echocancellation Circuit Analog Front End for Splitterless ADSL over ISDN

Overview The IEC-4-AFE-X Version 3.2 is part of Infineon´s chip set for a splitterless, FDD (non-overlapped) ADSL over ISDN linecard based on GEMINAX MAX according to Ref [3.], chapter 4.2.2 of Ref [5.], Annex B of Ref [6.] / Ref [7.], and Ref [8.]. Figure 1 shows the basic architecture of an in