CDCVF25081 3.3-V Phased-Lock Loop Clock Driver

1 Features • Phase-locked loop based, zero-delay buffer – 1 clock input to 2 banks of 4 outputs – No external RC network required • Supply voltage: 3 V to 3.6 V • Operating frequency: 8 MHz to 200 MHz • Low additive jitter (cycle-cycle): ±100 ps for 66 MHz to 200 MHz • Power-down mode avai

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 包装：管件 描述：IC 1:8 3.3V PLL CLK-DRVR 16-SOIC 集成电路（IC） 时钟发生器，PLL，频率合成器

3.3-V PHASED-LOCK LOOP CLOCK DRIVER

文件：596.43 Kbytes Page：16 Pages

CDCVF25081 3.3-V Phased-Lock Loop Clock Driver

1 Features • Phase-locked loop based, zero-delay buffer – 1 clock input to 2 banks of 4 outputs – No external RC network required • Supply voltage: 3 V to 3.6 V • Operating frequency: 8 MHz to 200 MHz • Low additive jitter (cycle-cycle): ±100 ps for 66 MHz to 200 MHz • Power-down mode avai

3.3-V PHASED-LOCK LOOP CLOCK DRIVER

文件：161.19 Kbytes Page：12 Pages

3.3-V PHASED-LOCK LOOP CLOCK DRIVER

文件：596.43 Kbytes Page：16 Pages

3.3-V PHASED-LOCK LOOP CLOCK DRIVER

文件：596.43 Kbytes Page：16 Pages

3.3-V PHASED-LOCK LOOP CLOCK DRIVER

文件：596.43 Kbytes Page：16 Pages

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 包装：卷带（TR） 描述：IC 1:8 3.3V PLL CLK-DRVR 16-SOIC 集成电路（IC） 时钟发生器，PLL，频率合成器

CDCVF25081 3.3-V Phased-Lock Loop Clock Driver

1 Features • Phase-locked loop based, zero-delay buffer – 1 clock input to 2 banks of 4 outputs – No external RC network required • Supply voltage: 3 V to 3.6 V • Operating frequency: 8 MHz to 200 MHz • Low additive jitter (cycle-cycle): ±100 ps for 66 MHz to 200 MHz • Power-down mode avai

3.3-V PHASED-LOCK LOOP CLOCK DRIVER

文件：596.43 Kbytes Page：16 Pages