CDCVF25081 3.3-V Phased-Lock Loop Clock Driver

1 Features • Phase-locked loop based, zero-delay buffer – 1 clock input to 2 banks of 4 outputs – No external RC network required • Supply voltage: 3 V to 3.6 V • Operating frequency: 8 MHz to 200 MHz • Low additive jitter (cycle-cycle): ±100 ps for 66 MHz to 200 MHz • Power-down mode avai

1:8 3.3V 锁相环路时钟驱动器

The CDCVF25081 is a high-performance, low-skew, low-jitter, phase-lock loop clock driver. It uses a PLL to precisely align, in both frequency and phase, the output clocks to the input clock signal. The CDCVF25081 operates from a nominal supply voltage of 3.3 V. The device also includes integrated se • Phase-Locked Loop-Based Zero-Delay Buffer\n• Operating Frequency: 10 MHz to 200 MHz\n• Low Jitter (Cycle-Cycle): ±100 ps Over the Range 66 MHz to 200 MHz\n• Distributes One Clock Input to Two Banks of Four Outputs\n• Auto Frequency Detection to Disable Device (Power Down Mode)\n• Consumes Less Tha;

3.3-V PHASED-LOCK LOOP CLOCK DRIVER

文件：161.19 Kbytes Page：12 Pages

3.3-V PHASED-LOCK LOOP CLOCK DRIVER

文件：596.43 Kbytes Page：16 Pages

丝印代码：CKV25081；CDCVF25081 3.3-V Phased-Lock Loop Clock Driver

1 Features • Phase-locked loop based, zero-delay buffer – 1 clock input to 2 banks of 4 outputs – No external RC network required • Supply voltage: 3 V to 3.6 V • Operating frequency: 8 MHz to 200 MHz • Low additive jitter (cycle-cycle): ±100 ps for 66 MHz to 200 MHz • Power-down mode avai

丝印代码：CKV25081；CDCVF25081 3.3-V Phased-Lock Loop Clock Driver

1 Features • Phase-locked loop based, zero-delay buffer – 1 clock input to 2 banks of 4 outputs – No external RC network required • Supply voltage: 3 V to 3.6 V • Operating frequency: 8 MHz to 200 MHz • Low additive jitter (cycle-cycle): ±100 ps for 66 MHz to 200 MHz • Power-down mode avai

丝印代码：CK081；CDCVF25081 3.3-V Phased-Lock Loop Clock Driver

1 Features • Phase-locked loop based, zero-delay buffer – 1 clock input to 2 banks of 4 outputs – No external RC network required • Supply voltage: 3 V to 3.6 V • Operating frequency: 8 MHz to 200 MHz • Low additive jitter (cycle-cycle): ±100 ps for 66 MHz to 200 MHz • Power-down mode avai

丝印代码：CK081；CDCVF25081 3.3-V Phased-Lock Loop Clock Driver

1 Features • Phase-locked loop based, zero-delay buffer – 1 clock input to 2 banks of 4 outputs – No external RC network required • Supply voltage: 3 V to 3.6 V • Operating frequency: 8 MHz to 200 MHz • Low additive jitter (cycle-cycle): ±100 ps for 66 MHz to 200 MHz • Power-down mode avai

丝印代码：CK081；CDCVF25081 3.3-V Phased-Lock Loop Clock Driver

1 Features • Phase-locked loop based, zero-delay buffer – 1 clock input to 2 banks of 4 outputs – No external RC network required • Supply voltage: 3 V to 3.6 V • Operating frequency: 8 MHz to 200 MHz • Low additive jitter (cycle-cycle): ±100 ps for 66 MHz to 200 MHz • Power-down mode avai

丝印代码：CK081；CDCVF25081 3.3-V Phased-Lock Loop Clock Driver

1 Features • Phase-locked loop based, zero-delay buffer – 1 clock input to 2 banks of 4 outputs – No external RC network required • Supply voltage: 3 V to 3.6 V • Operating frequency: 8 MHz to 200 MHz • Low additive jitter (cycle-cycle): ±100 ps for 66 MHz to 200 MHz • Power-down mode avai

丝印代码：CK081；CDCVF25081 3.3-V Phased-Lock Loop Clock Driver

1 Features • Phase-locked loop based, zero-delay buffer – 1 clock input to 2 banks of 4 outputs – No external RC network required • Supply voltage: 3 V to 3.6 V • Operating frequency: 8 MHz to 200 MHz • Low additive jitter (cycle-cycle): ±100 ps for 66 MHz to 200 MHz • Power-down mode avai

丝印代码：CK081；CDCVF25081 3.3-V Phased-Lock Loop Clock Driver

1 Features • Phase-locked loop based, zero-delay buffer – 1 clock input to 2 banks of 4 outputs – No external RC network required • Supply voltage: 3 V to 3.6 V • Operating frequency: 8 MHz to 200 MHz • Low additive jitter (cycle-cycle): ±100 ps for 66 MHz to 200 MHz • Power-down mode avai

3.3-V PHASED-LOCK LOOP CLOCK DRIVER

文件：596.43 Kbytes Page：16 Pages

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 包装：卷带（TR） 描述：IC 1:8 3.3V PLL CLK-DRVR 16-SOIC 集成电路（IC） 时钟发生器，PLL，频率合成器

3.3-V PHASED-LOCK LOOP CLOCK DRIVER

文件：596.43 Kbytes Page：16 Pages

3.3-V PHASED-LOCK LOOP CLOCK DRIVER

文件：596.43 Kbytes Page：16 Pages

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 包装：管件 描述：IC 1:8 3.3V PLL CLK-DRVR 16-SOIC 集成电路（IC） 时钟发生器，PLL，频率合成器

3.3-V PHASED-LOCK LOOP CLOCK DRIVER

文件：596.43 Kbytes Page：16 Pages

3.3-V PHASED-LOCK LOOP CLOCK DRIVER

文件：596.43 Kbytes Page：16 Pages

3.3-V PHASED-LOCK LOOP CLOCK DRIVER

文件：596.43 Kbytes Page：16 Pages

3.3-V PHASED-LOCK LOOP CLOCK DRIVER

文件：596.43 Kbytes Page：16 Pages

3.3-V PHASED-LOCK LOOP CLOCK DRIVER

文件：596.43 Kbytes Page：16 Pages

3.3-V PHASED-LOCK LOOP CLOCK DRIVER

文件：596.43 Kbytes Page：16 Pages