2.5-V PHASE LOCK LOOP CLOCK DRIVER

文件：389.52 Kbytes Page：16 Pages

封装/外壳：48-TFSOP（0.240"，6.10mm 宽） 包装：托盘 描述：IC SSTL-II PLL CLK-DRVR 48-TSSOP 集成电路（IC） 时钟发生器，PLL，频率合成器

封装/外壳：48-TFSOP（0.240"，6.10mm 宽） 包装：卷带（TR） 描述：IC SSTL-II PLL CLK-DRVR 48TSSOP 集成电路（IC） 时钟发生器，PLL，频率合成器

2.5-V PHASE LOCK LOOP CLOCK DRIVER

文件：389.52 Kbytes Page：16 Pages

857 Series High Temp Card Edge Connector | Black | 0.156 (3.96mm) Pitch | 0.200 (5.08mm) Row Spacing | Low Profile Insulator

Features 0.156 (3.96mm) Contact Spacing by 0.200 (5.08mm) Row Spacing Accepts .062 (1.57mm) Nominal Thickness P.C. Board Low Profile Insulator Body, 0.473 (12.01mm) Contact Termination Options include P.C. Tail, Wire Hole, Wire Wrap, 90 and Extender Board Bends Single or Dual Row Configuratio

General Purpose Transistor

Features - Low current (max. 100mA). - Low voltage. - AEC-Q101 Qualified.

General Purpose Transistor

Features - For AF input stages and driver applications. - High current gain. - Low collector-emitter saturation voltage. - Low noise between 30Hz and 15kHz. - AEC-Q101 Qualified.

General Purpose Transistor

Features - Low current (max. 100mA). - Low voltage. - AEC-Q101 Qualified.

boxes and ancillary products

文件：3.51246 Mbytes Page：5 Pages