丝印代码：2102；CDCLVP2102 Four-LVPECL Output, High-Performance Clock Buffer

1 Features 1• Dual 1:2 Differential Buffer • Two Clock Inputs • Universal Inputs Can Accept LVPECL, LVDS, LVCMOS/LVTTL • Four LVPECL Outputs • Maximum Clock Frequency: 2 GHz • Maximum Core Current Consumption: 48 mA • Very Low Additive Jitter:

丝印代码：2102；CDCLVP2102 Four-LVPECL Output, High-Performance Clock Buffer

1 Features 1• Dual 1:2 Differential Buffer • Two Clock Inputs • Universal Inputs Can Accept LVPECL, LVDS, LVCMOS/LVTTL • Four LVPECL Outputs • Maximum Clock Frequency: 2 GHz • Maximum Core Current Consumption: 48 mA • Very Low Additive Jitter:

Integrated Circuit NMOS, 1K Static RAM (SRAM), 350ns

Description: The NTE2101 is a high–speed 1024 x 1 bit static random access read/write memory in a 16–Lead DIP type package designed using N–Channel depletion mode silicon gate technology. Static storage cells eliminate the need for clock or refresh circuitry. Low threshold silicon gate N–Cha

SYSTEM RESET IC

文件：314.14 Kbytes Page：11 Pages

SYSTEM RESET IC

文件：314.14 Kbytes Page：11 Pages

SYSTEM RESET IC

文件：314.14 Kbytes Page：11 Pages

SYSTEM RESET IC

文件：314.14 Kbytes Page：11 Pages