Dual 1:2 Low Additive Jitter LVDS Buffer

1FEATURES • Dual 1:2 Differential Buffer • Low Additive Jitter

CDCLVP2102 Four-LVPECL Output, High-Performance Clock Buffer

1 Features 1• Dual 1:2 Differential Buffer • Two Clock Inputs • Universal Inputs Can Accept LVPECL, LVDS, LVCMOS/LVTTL • Four LVPECL Outputs • Maximum Clock Frequency: 2 GHz • Maximum Core Current Consumption: 48 mA • Very Low Additive Jitter:

Dual supply translating transceiver; open-drain; auto direction sensing

SINGLE-CHIP USB-TO-UART BRIDGE

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