丝印代码：CDC516；3.3-V PHASE-LOCK LOOP CLOCK DRIVER

Use CDCVF2510A as a Replacement for this Device Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications Distributes One Clock Input to Four Banks of Four Outputs Separate Output Enable for Each Output Bank External Feedback Pin (FBIN) Is Used to Synchronize the Outputs to the

丝印代码：CDC516；3.3-V PHASE-LOCK LOOP CLOCK DRIVER

Use CDCVF2510A as a Replacement for this Device Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications Distributes One Clock Input to Four Banks of Four Outputs Separate Output Enable for Each Output Bank External Feedback Pin (FBIN) Is Used to Synchronize the Outputs to the

丝印代码：CDC516；3.3-V PHASE-LOCK LOOP CLOCK DRIVER

Use CDCVF2510A as a Replacement for this Device Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications Distributes One Clock Input to Four Banks of Four Outputs Separate Output Enable for Each Output Bank External Feedback Pin (FBIN) Is Used to Synchronize the Outputs to the

丝印代码：CDC516；3.3-V PHASE-LOCK LOOP CLOCK DRIVER

Use CDCVF2510A as a Replacement for this Device Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications Distributes One Clock Input to Four Banks of Four Outputs Separate Output Enable for Each Output Bank External Feedback Pin (FBIN) Is Used to Synchronize the Outputs to the

丝印代码：CDC516；3.3-V PHASE-LOCK LOOP CLOCK DRIVER

Use CDCVF2510A as a Replacement for this Device Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications Distributes One Clock Input to Four Banks of Four Outputs Separate Output Enable for Each Output Bank External Feedback Pin (FBIN) Is Used to Synchronize the Outputs to the

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

Use CDCVF2510A as a Replacement for this Device Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications Distributes One Clock Input to Four Banks of Four Outputs Separate Output Enable for Each Output Bank External Feedback Pin (FBIN) Is Used to Synchronize the Outputs to the

具有三态输出的 3.3V 相位锁定环路时钟驱动器

The CDC516 is a high-performance, low-skew, low-jitter, phase-lock loop clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the feedback output (FBOUT) to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDC516 o • Use CDCVF2510A as a Replacement for this Device\n• Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications\n• Distributes One Clock Input to Four Banks of Four Outputs\n• Separate Output Enable for Each Output Bank\n• External Feedback Pin (FBIN) Is Used to Synchronize the Outputs to ;

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

文件：160.08 Kbytes Page：11 Pages

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

文件：160.08 Kbytes Page：11 Pages

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

文件：160.08 Kbytes Page：11 Pages

封装/外壳：48-TFSOP（0.240"，6.10mm 宽） 包装：卷带（TR） 描述：IC PLL CLOCK DVR 3.3V 48-TSSOP 集成电路（IC） 时钟发生器，PLL，频率合成器

封装/外壳：48-TFSOP（0.240"，6.10mm 宽） 包装：托盘 描述：IC 3.3V PLL CLK DRVR 3ST 48TSSOP 集成电路（IC） 时钟发生器，PLL，频率合成器

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

文件：160.08 Kbytes Page：11 Pages

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

文件：160.08 Kbytes Page：11 Pages

Numeric Display

文件：21.07 Kbytes Page：1 Pages

Numeric Display

文件：21.07 Kbytes Page：1 Pages

Numeric Display

文件：21.26 Kbytes Page：1 Pages

Numeric Display

文件：21.07 Kbytes Page：1 Pages

Numeric Display

文件：21.26 Kbytes Page：1 Pages