3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS

FEATURES · Low Output Skew for Clock-Distribution and Clock-Generation Applications · Operates at 3.3-V VCC · Distributes One Clock Input to Six Outputs · One Select Input Configures Three Outputs to Operate at One-Half or Double the Input Frequency · No External RC Network Required · On-

封装/外壳：28-SSOP（0.209"，5.30mm 宽） 包装：管件 描述：IC 3.3V PLL CLK-DRVR 28-SSOP 集成电路（IC） 时钟发生器，PLL，频率合成器

3.3V PHASE-LOCK LOOP CLOCK DRIVER

文件：490.18 Kbytes Page：15 Pages

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS

文件：143.79 Kbytes Page：10 Pages

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS

FEATURES · Low Output Skew for Clock-Distribution and Clock-Generation Applications · Operates at 3.3-V VCC · Distributes One Clock Input to Six Outputs · One Select Input Configures Three Outputs to Operate at One-Half or Double the Input Frequency · No External RC Network Required · On-

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS

FEATURES · Low Output Skew for Clock-Distribution and Clock-Generation Applications · Operates at 3.3-V VCC · Distributes One Clock Input to Six Outputs · One Select Input Configures Three Outputs to Operate at One-Half or Double the Input Frequency · No External RC Network Required · On-

3.3V PHASE-LOCK LOOP CLOCK DRIVER

文件：490.18 Kbytes Page：15 Pages

封装/外壳：28-SSOP（0.209"，5.30mm 宽） 包装：卷带（TR） 描述：IC 3.3V PLL CLK-DRVR 28-SSOP 集成电路（IC） 时钟发生器，PLL，频率合成器

3.3V PHASE-LOCK LOOP CLOCK DRIVER

文件：490.18 Kbytes Page：15 Pages

3.3V PHASE-LOCK LOOP CLOCK DRIVER

文件：490.18 Kbytes Page：15 Pages

USB DUAL POWER CONTROL SWITCHES

The A2526EL/M and A2536EL/M are integrated high-side dual power switches, optimized for self-powered and bus-powered Universal Serial Bus (USB) applications. Few external components are necessary to satisfy USB requirements. The A2526EL/EM ENABLE inputs are active high; the A2536EL/EM are active l

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文件：132.1 Kbytes Page：1 Pages

Break-Away Bumpers

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Premier Supplier of Electronic Hardware

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