丝印代码：CDC2536；3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS

FEATURES · Low Output Skew for Clock-Distribution and Clock-Generation Applications · Operates at 3.3-V VCC · Distributes One Clock Input to Six Outputs · One Select Input Configures Three Outputs to Operate at One-Half or Double the Input Frequency · No External RC Network Required · On-

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS

文件：143.79 Kbytes Page：10 Pages

3.3V PHASE-LOCK LOOP CLOCK DRIVER

文件：490.18 Kbytes Page：15 Pages

封装/外壳：28-SSOP（0.209"，5.30mm 宽） 包装：管件 描述：IC 3.3V PLL CLK-DRVR 28-SSOP 集成电路（IC） 时钟发生器，PLL，频率合成器

丝印代码：CDC2536；3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS

FEATURES · Low Output Skew for Clock-Distribution and Clock-Generation Applications · Operates at 3.3-V VCC · Distributes One Clock Input to Six Outputs · One Select Input Configures Three Outputs to Operate at One-Half or Double the Input Frequency · No External RC Network Required · On-

丝印代码：CDC2536；3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS

FEATURES · Low Output Skew for Clock-Distribution and Clock-Generation Applications · Operates at 3.3-V VCC · Distributes One Clock Input to Six Outputs · One Select Input Configures Three Outputs to Operate at One-Half or Double the Input Frequency · No External RC Network Required · On-

3.3V PHASE-LOCK LOOP CLOCK DRIVER

文件：490.18 Kbytes Page：15 Pages

封装/外壳：28-SSOP（0.209"，5.30mm 宽） 包装：卷带（TR） 描述：IC 3.3V PLL CLK-DRVR 28-SSOP 集成电路（IC） 时钟发生器，PLL，频率合成器

3.3V PHASE-LOCK LOOP CLOCK DRIVER

文件：490.18 Kbytes Page：15 Pages

3.3V PHASE-LOCK LOOP CLOCK DRIVER

文件：490.18 Kbytes Page：15 Pages

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS

文件：143.79 Kbytes Page：10 Pages

Silicon Complementary Transistors High Current Switch

Features: • High Current Capacity • Wide ASO Range • Low Saturation Voltage Applications: • Motor Drivers • Relay Drivers • Converters

SDH/SONET STM16/OC48 demultiplexer

DESCRIPTION The OQ2536HP is a 32-channel demultiplexer intended for use in STM16/OC48 applications. It demultiplexes a single 2.5 Gbits/s input channel to 32 × 78 Mbits/s output channels. The data and clock outputs on the low speed interface are GTL compatible, while the high speed data and clock

Commercial, Industrial Quad 1 to 4 Clock Drivers

文件：127.42 Kbytes Page：8 Pages

Commercial, Industrial Quad 1 to 4 Clock Drivers

文件：127.42 Kbytes Page：8 Pages