3.3-V PHASE-LOCK LOOP CLOCK DRIVER

Use CDCVF2509A as a Replacement for this Device Designed to Meet PC SDRAM Registered DIMM Specification Spread Spectrum Clock Compatible Operating Frequency 25 MHz to 125 MHz Phase Error Time Minus Jitter at 66 MHz to 100 MHz Is ±150 ps Jitter (peak − peak) at 66 MHz to 100 MHz Is ±80 ps

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

文件：147.04 Kbytes Page：10 Pages

丝印代码：CK2509B；3.3-V PHASE-LOCK LOOP CLOCK DRIVER

Use CDCVF2509A as a Replacement for this Device Designed to Meet PC SDRAM Registered DIMM Specification Spread Spectrum Clock Compatible Operating Frequency 25 MHz to 125 MHz Phase Error Time Minus Jitter at 66 MHz to 100 MHz Is ±150 ps Jitter (peak − peak) at 66 MHz to 100 MHz Is ±80 ps

丝印代码：CK2509B；3.3-V PHASE-LOCK LOOP CLOCK DRIVER

Use CDCVF2509A as a Replacement for this Device Designed to Meet PC SDRAM Registered DIMM Specification Spread Spectrum Clock Compatible Operating Frequency 25 MHz to 125 MHz Phase Error Time Minus Jitter at 66 MHz to 100 MHz Is ±150 ps Jitter (peak − peak) at 66 MHz to 100 MHz Is ±80 ps

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

文件：147.04 Kbytes Page：10 Pages

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

文件：631.52 Kbytes Page：14 Pages

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

文件：631.52 Kbytes Page：14 Pages

封装/外壳：24-TSSOP（0.173"，4.40mm 宽） 包装：托盘 描述：IC PLL CLOCK DVR 3.3V 24-TSSOP 集成电路（IC） 时钟发生器，PLL，频率合成器

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

文件：631.52 Kbytes Page：14 Pages

封装/外壳：24-TSSOP（0.173"，4.40mm 宽） 包装：管件 描述：IC 3.3V PLL CLK-DRVR 24-TSSOP 集成电路（IC） 时钟发生器，PLL，频率合成器

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

文件：631.52 Kbytes Page：14 Pages

50-150 MHz 1:9 SDRAM clock driver

DESCRIPTION The PCK2509S is a high-performance, low-skew, low-jitter, phase-locked loop (PLL) clock driver. It uses a PLLto precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The PC

50-150 MHz 1:9 SDRAM clock driver

DESCRIPTION The PCK2509SA is a high-performance, low-skew, low-jitter, phase-locked loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The

50-150 MHz 1:9 SDRAM clock driver

DESCRIPTION The PCK2509S is a high-performance, low-skew, low-jitter, phase-locked loop (PLL) clock driver. It uses a PLLto precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The PC

VIDEO SUPER INPOSER WITH Y-C MIXER

文件：194 Kbytes Page：5 Pages

VIDEO SUPER INPOSER WITH Y-C MIXER

文件：194 Kbytes Page：5 Pages