High-Speed CMOS Logic Octal Inverting Transparent Latch, Three-State Outputs

Features • Common Latch-Enable Control • Common Three-State Output Enable Control • Buffered Inputs • Three-State Outputs • Bus Line Driving Capacity • Typical Propagation Delay = 13ns at VCC = 5V, CL = 15pF, TA = 25oC (Data to Output) • Fanout (Over Temperature Range) - Standard Outputs

High-Speed CMOS Logic Octal Inverting Transparent Latch, Three-State Outputs

Features • Common Latch-Enable Control • Common Three-State Output Enable Control • Buffered Inputs • Three-State Outputs • Bus Line Driving Capacity • Typical Propagation Delay = 13ns at VCC = 5V, CL = 15pF, TA = 25oC (Data to Output) • Fanout (Over Temperature Range) - Standard Outputs

High Speed CMOS Logic Octal Inverting Transparent Latch, Three-State Outputs

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High-Speed CMOS Logic Octal Inverting Transparent Latch, Three-State Outputs

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High-Speed CMOS Logic Octal Inverting Transparent Latch, Three-State Outputs

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Octal D-type transparent latch; 3-state; inverting

GENERAL DESCRIPTION The 74HC/HCT563 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no.7A. The 74HC/HCT563 are octal D-type transparent latches featuring separate D-type inputs for each latch